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4114 Commits

Author SHA1 Message Date
Craig Topper
2c492a1861 Make custom operand parsing mnemonic indices use the same mnemonic table as the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets. 
llvm-svn: 164109
 2012-09-18 07:02:21 +00:00
Craig Topper
c4107aa8c2 Use variable type for index into mnemonic table. Shrinks size of index field on in tree targets. Saving static data space. 
llvm-svn: 164108
 2012-09-18 06:10:45 +00:00
Andrew Trick
6cba50cbb4 Replaced ReInitMCSubtargetInfo with InitMCProcessor. 
Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.

llvm-svn: 164105
 2012-09-18 05:33:15 +00:00
Andrew Trick
73e100e6f5 comment typo 
llvm-svn: 164097
 2012-09-18 04:03:30 +00:00
Andrew Trick
418db6184f TableGen subtarget emitter. Use getSchedClassIdx. 
llvm-svn: 164096
 2012-09-18 03:55:55 +00:00
Andrew Trick
b7b658d440 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants. 
llvm-svn: 164095
 2012-09-18 03:41:43 +00:00
Andrew Trick
c2ee4420fd TableGen subtarget emitter. Remove unnecessary header dependence. 
llvm-svn: 164094
 2012-09-18 03:32:57 +00:00
Andrew Trick
65c7aae93f TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
llvm-svn: 164092
 2012-09-18 03:18:56 +00:00
Craig Topper
24762462b0 Mark asm matcher conversion table as const. 
llvm-svn: 164088
 2012-09-18 01:41:49 +00:00
Craig Topper
5f44668251 Fix typo in comment. No functional change. 
llvm-svn: 164086
 2012-09-18 01:13:36 +00:00
Andrew Trick
2b04a12c0c Backout the wrong subtarget emitter fix 
llvm-svn: 164078
 2012-09-17 23:14:15 +00:00
Andrew Trick
1956ad7efe Fix release build after reverting 
llvm-svn: 164075
 2012-09-17 23:05:04 +00:00
Andrew Trick
150c97940b Revert r164061-r164067. Most of the new subtarget emitter. 
I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072
 2012-09-17 23:00:42 +00:00
Andrew Trick
9400ee3c79 InitMCProcessor 
llvm-svn: 164066
 2012-09-17 22:19:12 +00:00
Andrew Trick
81e5a058f2 comment typo 
llvm-svn: 164064
 2012-09-17 22:19:04 +00:00
Andrew Trick
22072f5bf2 TableGen subtarget emitter. Use getSchedClassIdx. 
llvm-svn: 164063
 2012-09-17 22:19:01 +00:00
Andrew Trick
7403ff5282 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants. 
llvm-svn: 164062
 2012-09-17 22:18:58 +00:00
Andrew Trick
8a499d1f62 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
llvm-svn: 164061
 2012-09-17 22:18:55 +00:00
Andrew Trick
f5182127b1 TableGen subtarget emitter. Format and emit data tables for the new machine model. 
llvm-svn: 164060
 2012-09-17 22:18:50 +00:00
Andrew Trick
ef09f46517 TableGen subtarget emitter. Generate data tables for the new machine model. 
Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

llvm-svn: 164059
 2012-09-17 22:18:48 +00:00
Andrew Trick
cf41195b6a TableGen subtarget emitter. Emit processor resources for the new machine model. 
llvm-svn: 164058
 2012-09-17 22:18:45 +00:00
Andrew Trick
d15e58e200 TableGen subtarget parser: Add getProcResourcesIdx(). 
llvm-svn: 164057
 2012-09-17 22:18:43 +00:00
Jim Grosbach
68def8a302 TableGen: Add initializer. 
Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.

llvm-svn: 164041
 2012-09-17 18:00:53 +00:00
Axel Naumann
bcdf671ac4 Fix a few vars that can end up being used without initialization. 
The cases where no initialization happens should still be checked for logic flaws.

llvm-svn: 164032
 2012-09-17 14:20:57 +00:00
Michael Liao
00438be1a0 Fix typo 
llvm-svn: 164012
 2012-09-17 04:43:39 +00:00
Craig Topper
5e50ef6b15 Add 'virtual' keywoards to output file for overridden functions. 
llvm-svn: 164002
 2012-09-16 18:25:36 +00:00
Craig Topper
f3580aa31e Add 'virtual' keywoards to output file for overridden functions. 
llvm-svn: 163999
 2012-09-16 16:35:22 +00:00
Dmitri Gribenko
dd5d6c0da7 Fix Doxygen issues: wrap code examples in \code and use \p to refer to 
parameters.

llvm-svn: 163984
 2012-09-15 20:22:05 +00:00
Craig Topper
7989d0ccdc Revert r163878 as it breaks on targets with alternate register names. Such targets do not exist in the main tree so this was not noticed. 
llvm-svn: 163959
 2012-09-15 01:22:42 +00:00
Andrew Trick
25c8faee30 TableGen subtarget parser. Handle new machine model. 
Collect processor resources from the subtarget defs.

llvm-svn: 163953
 2012-09-15 00:20:02 +00:00
Andrew Trick
0587f1d794 TableGen subtarget parser. Handle new machine model. 
Infer SchedClasses from variants defined by the target or subtarget.

llvm-svn: 163952
 2012-09-15 00:19:59 +00:00
Andrew Trick
b324ff57ad TableGen subtarget parser. Handle new machine model. 
Collect SchedClasses and SchedRW types from the subtarget defs.

llvm-svn: 163951
 2012-09-15 00:19:57 +00:00
Craig Topper
0320f5eded Allow the second opcode info table to be 8, 16, or 32-bits as needed to represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands. 
llvm-svn: 163880
 2012-09-14 08:33:11 +00:00
Craig Topper
5cd6b912e7 Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead. 
llvm-svn: 163878
 2012-09-14 06:37:49 +00:00
Manman Ren
782be257ee AsmWriterEmitter: OpInfo2 should be unsigned 16-bit. 
Fix an issue in r163814.

llvm-svn: 163837
 2012-09-13 20:47:48 +00:00
Manman Ren
4b62c95592 AsmWriterEmitter: increase the number of bits for OpcodeInfo from 32-bit to 
48-bit if necessary, in order to reduce the generated code size.

We have 900 cases not covered by OpcodeInfo in ATT AsmWriter and more in Intel
AsmWriter and ARM AsmWriter.

This patch reduced the clang Release build size by 50k, running on a Mac Pro.

llvm-svn: 163814
 2012-09-13 17:43:46 +00:00
Dmitri Gribenko
aee81e7cae Fix Doxygen issues: 
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
  people want -- it starts a new paragraph).

llvm-svn: 163790
 2012-09-13 12:34:29 +00:00
Craig Topper
e2e98bb26b Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. 
llvm-svn: 163774
 2012-09-13 05:45:42 +00:00
Jim Grosbach
adfdb46f2c TableGen: Convert an assert() to a proper diagnostic. 
llvm-svn: 163726
 2012-09-12 17:40:25 +00:00
Dmitri Gribenko
8982c8a34d Fix a couple of Doxygen comment issues pointed out by -Wdocumentation. 
llvm-svn: 163721
 2012-09-12 16:59:47 +00:00
Owen Anderson
e42d2ba20d Improve tblgen code cleanliness: create an unknown_class, from which the unknown def inherits. Make tblgen check for that class, rather than checking for the def itself. 
llvm-svn: 163664
 2012-09-11 23:47:08 +00:00
Owen Anderson
8aa2a6cbb7 Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name. 
llvm-svn: 163659
 2012-09-11 23:32:17 +00:00
Jakob Stoklund Olesen
8a149baa44 Add TRI::getSubRegIndexLaneMask(). 
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.

The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.

Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.

llvm-svn: 163630
 2012-09-11 16:34:08 +00:00
Jakob Stoklund Olesen
d2bb5cf28e Clean the sub-reg index composition maps at emission. 
Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.

llvm-svn: 163629
 2012-09-11 16:34:05 +00:00
Jakob Stoklund Olesen
1e7f74aaa8 Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges. 
Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.

llvm-svn: 163628
 2012-09-11 16:34:02 +00:00
Craig Topper
c9fd7a1602 Change unsigned to a uint16_t in static disassembler tables to reduce the table size. 
llvm-svn: 163594
 2012-09-11 04:19:21 +00:00
Evgeniy Stepanov
24b5faa541 GTest on Android needs a custom tmpdir path. 
llvm-svn: 163501
 2012-09-10 10:32:29 +00:00
NAKAMURA Takumi
57a661f79f lit: Util.which(): Use os.path.isfile() instead of os.path.exists(), or it hits to the directory. 
For example, which('loop-convert') returns 'loop-convert' when the directory 'loop-convert' exists.

llvm-svn: 163469
 2012-09-08 12:07:24 +00:00
Ted Kremenek
4440f8539f Revert "Add -exact-match option to FileCheck to allow clients to do exact matches without using regular expressions." 
Turns out I did not need it after all.  If we find a use for it in the future, we
can resurrect it.

llvm-svn: 163457
 2012-09-08 04:32:13 +00:00
Anshuman Dasgupta
5b2793f0a5 Refactored DFA generator. Merged transition class into state class. 
Patch by Ivan Llopard!

llvm-svn: 163424
 2012-09-07 21:35:43 +00:00