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Commit Graph

8462 Commits

Author SHA1 Message Date
Anton Korobeynikov
6a779ad6fa Add one more 'magic' define :)
llvm-svn: 52420
2008-06-17 17:57:43 +00:00
Anton Korobeynikov
cdfbb1eae5 Unbreak non-PPC builds
llvm-svn: 52419
2008-06-17 17:38:31 +00:00
Anton Korobeynikov
5b04f6d658 Provide generic hooks for icache invalidation. Add PPC implementation.
Patch by Gary Benson!

llvm-svn: 52418
2008-06-17 17:30:05 +00:00
Evan Cheng
89e2e3292d Rather than avoiding to wrap ISD::DECLARE GV operand in X86ISD::Wrapper, simply handle it at dagisel time with x86 specific isel code.
llvm-svn: 52377
2008-06-17 02:01:22 +00:00
Evan Cheng
4e7b7b21a2 Horizontal-add instructions are not commutative.
llvm-svn: 52363
2008-06-16 21:16:24 +00:00
Evan Cheng
acd614c262 mpsadbw is commutable.
llvm-svn: 52352
2008-06-16 20:25:59 +00:00
Chris Lattner
ddfa0590ae Add support for icache invalidation on non-darwin ppc systems.
Patch by Gary Benson!

llvm-svn: 52332
2008-06-16 17:04:06 +00:00
Evan Cheng
2dfe8c2435 Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
llvm-svn: 52308
2008-06-16 07:33:11 +00:00
Chris Lattner
0b945db11c Switch from generating the int128 typedefs based on targetdata to generating
them based on the end-compiler's capabilities.  This fixes PR2453

llvm-svn: 52297
2008-06-16 04:25:29 +00:00
Andrew Lenharth
327c3e7559 add missing atomic intrinsic from gcc
llvm-svn: 52270
2008-06-14 05:48:15 +00:00
Duncan Sands
40c8db881a Disable some DAG combiner optimizations that may be
wrong for volatile loads and stores.  In fact this
is almost all of them!  There are three types of
problems: (1) it is wrong to change the width of
a volatile memory access.  These may be used to
do memory mapped i/o, in which case a load can have
an effect even if the result is not used.  Consider
loading an i32 but only using the lower 8 bits.  It
is wrong to change this into a load of an i8, because
you are no longer tickling the other three bytes.  It
is also unwise to make a load/store wider.  For
example, changing an i16 load into an i32 load is
wrong no matter how aligned things are, since the
fact of loading an additional 2 bytes can have
i/o side-effects.  (2) it is wrong to change the
number of volatile load/stores: they may be counted
by the hardware.  (3) it is wrong to change a volatile
load/store that requires one memory access into one
that requires several.  For example on x86-32, you
can store a double in one processor operation, but to
store an i64 requires two (two i32 stores).  In a
multi-threaded program you may want to bitcast an i64
to a double and store as a double because that will
occur atomically, and be indivisible to other threads.
So it would be wrong to convert the store-of-double
into a store of an i64, because this will become two
i32 stores - no longer atomic.  My policy here is
to say that the number of processor operations for
an illegal operation is undefined.  So it is alright
to change a store of an i64 (requires at least two
stores; but could be validly lowered to memcpy for
example) into a store of double (one processor op).
In short, if the new store is legal and has the same
size then I say that the transform is ok.  It would
also be possible to say that transforms are always
ok if before they were illegal, whether after they
are illegal or not, but that's more awkward to do
and I doubt it buys us anything much.
However this exposed an interesting thing - on x86-32
a store of i64 is considered legal!  That is because
operations are marked legal by default, regardless of
whether the type is legal or not.  In some ways this
is clever: before type legalization this means that
operations on illegal types are considered legal;
after type legalization there are no illegal types
so now operations are only legal if they really are.
But I consider this to be too cunning for mere mortals.
Better to do things explicitly by testing AfterLegalize.
So I have changed things so that operations with illegal
types are considered illegal - indeed they can never
map to a machine operation.  However this means that
the DAG combiner is more conservative because before
it was "accidentally" performing transforms where the
type was illegal because the operation was nonetheless
marked legal.  So in a few such places I added a check
on AfterLegalize, which I suppose was actually just
forgotten before.  This causes the DAG combiner to do
slightly more than it used to, which resulted in the X86
backend blowing up because it got a slightly surprising
node it wasn't expecting, so I tweaked it.

llvm-svn: 52254
2008-06-13 19:07:40 +00:00
Anton Korobeynikov
74422b3cd0 Properly lower DYNAMIC_STACKALLOC - bracket all black magic with
CALLSEQ_BEGIN & CALLSEQ_END.

llvm-svn: 52225
2008-06-11 20:16:42 +00:00
Dan Gohman
ce662293ed CPPBackend support for extractvalue and insertvalue.
llvm-svn: 52147
2008-06-09 14:12:10 +00:00
Dan Gohman
ee7b8797d0 Abort on an unrecognized opcode.
llvm-svn: 52146
2008-06-09 14:09:13 +00:00
Dan Gohman
5f7b94fd7b Update the CPP backend for the ConstantFP::get API change.
llvm-svn: 52144
2008-06-09 14:08:11 +00:00
Rafael Espindola
feaadb1e05 add support for PIC on linux x86-64
llvm-svn: 52139
2008-06-09 09:52:31 +00:00
Duncan Sands
fe2a970a5c Remove comparison methods for MVT. The main cause
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits.  Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.

llvm-svn: 52098
2008-06-08 20:54:56 +00:00
Bruno Cardoso Lopes
c91758a7fc Added FP instruction formats.
llvm-svn: 52086
2008-06-08 01:39:36 +00:00
Bill Wendling
346669b97f Temporarily reverting r52056. It's causing PPC to fail to bootstrap.
llvm-svn: 52085
2008-06-08 01:36:24 +00:00
Bruno Cardoso Lopes
b0cb678a47 Added support for FP Registers
llvm-svn: 52079
2008-06-07 21:32:41 +00:00
Evan Cheng
6b5b097805 Revert r52046. It broke cbe on x86 / Mac OS X.
llvm-svn: 52071
2008-06-07 07:50:29 +00:00
Evan Cheng
b19baf81ba Typo.
llvm-svn: 52062
2008-06-06 21:00:10 +00:00
Evan Cheng
3ac5c6575a PPC preferred loop alignment is 16.
llvm-svn: 52056
2008-06-06 19:50:46 +00:00
Anton Korobeynikov
8c40a176f7 Handle assembler identifiers specially in CBE. This fixes PR2418.
llvm-svn: 52046
2008-06-06 16:08:26 +00:00
Duncan Sands
d634afe3aa Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044
2008-06-06 12:08:01 +00:00
Bruno Cardoso Lopes
23e9cfc581 Added custom isel for MUL, SDIVREM, UDIVREM, SMUL_LOHI and UMUL_LOHI nodes
MUL is not anymore directly matched because its a pseudoinstruction.
LogicI class fixed to zero-extend immediates. 

llvm-svn: 52036
2008-06-06 06:37:31 +00:00
Bruno Cardoso Lopes
7b58f690cb Added custom SELECT_CC lowering
Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC

llvm-svn: 52031
2008-06-06 00:58:26 +00:00
Evan Cheng
badbe3e3fa Don't break strict aliasing.
llvm-svn: 52026
2008-06-05 22:59:21 +00:00
Chris Lattner
7e3db1af97 Rewrite a bunch of the CBE's inline asm code, giving it the
ability to handle indirect input operands.  This fixes PR2407.

llvm-svn: 51952
2008-06-04 18:03:28 +00:00
Duncan Sands
5a6c6a92c1 Change packed struct layout so that field sizes
are the same as in unpacked structs, only field
positions differ.  This only matters for structs
containing x86 long double or an apint; it may
cause backwards compatibility problems if someone
has bitcode containing a packed struct with a
field of one of those types.
The issue is that only 10 bytes are needed to
hold an x86 long double: the store size is 10
bytes, but the ABI size is 12 or 16 bytes (linux/
darwin) which comes from rounding the store size
up by the alignment.  Because it seemed silly not
to pack an x86 long double into 10 bytes in a
packed struct, this is what was done.  I now
think this was a mistake.  Reserving the ABI size
for an x86 long double field even in a packed
struct makes things more uniform: the ABI size is
now always used when reserving space for a type.
This means that developers are less likely to
make mistakes.  It also makes life easier for the
CBE which otherwise could not represent all LLVM
packed structs (PR2402).
Front-end people might need to adjust the way
they create LLVM structs - see following change
to llvm-gcc.

llvm-svn: 51928
2008-06-04 08:21:45 +00:00
Bruno Cardoso Lopes
5a4d1d0fd3 Some Mips minor fixes
Added support for mips little endian arch => mipsel

llvm-svn: 51923
2008-06-04 01:45:25 +00:00
Dale Johannesen
c0cd6cd4d4 Add StringConstantPrefix to control what the
assembler names of string constants look like.

llvm-svn: 51909
2008-06-03 18:09:06 +00:00
Scott Michel
5323d58281 Add necessary 64-bit support so that gcc frontend compiles (mostly). Current
issue is operand promotion for setcc/select... but looks like the fundamental
stuff is implemented for CellSPU.

llvm-svn: 51884
2008-06-02 22:18:03 +00:00
Dan Gohman
5a9c2a3434 Implement CBE support for first-class structs and array values,
and insertvalue and extractvalue instructions.

First-class array values are not trivial because C doesn't
support them. The approach I took here is to wrap all arrays
in structs. Feedback is welcome.

The 2007-01-15-NamedArrayType.ll test needed to be modified
because it has a "not grep" for a string that now exists,
because array types now have associated struct types, and
those struct types have names.

llvm-svn: 51881
2008-06-02 21:30:49 +00:00
Rafael Espindola
feec40a71f Don't use the GOT for symbols that are not externally visible.
llvm-svn: 51865
2008-06-02 07:52:43 +00:00
Bruno Cardoso Lopes
e5b4a0d794 Fixed flag issue that was generating infinite loop while in list scheduling.
llvm-svn: 51833
2008-06-01 03:49:39 +00:00
Nick Lewycky
1bcd80adf7 Peer through sext/zext when looking for not(cmp).
llvm-svn: 51819
2008-05-31 19:01:33 +00:00
Nick Lewycky
566baa2c72 Yay us! Every one of these examples turns into icmp/zext/ret.
llvm-svn: 51818
2008-05-31 18:20:26 +00:00
Chris Lattner
43a47ddd89 Fix the CBE's handling of instructions whose result is an i1. Previously,
we did not truncate the value down to i1 with (x&1).  This caused a problem
when the computation of x was nontrivial, for example, "add i1 1, 1" would 
return 2 instead of 0.

This makes the testcase compile into:

...
  llvm_cbe_t = (((llvm_cbe_r == 0u) + (llvm_cbe_r == 0u))&1);
  llvm_cbe_u = (((unsigned int )(bool )llvm_cbe_t));
...

instead of:

...
  llvm_cbe_t = ((llvm_cbe_r == 0u) + (llvm_cbe_r == 0u));
  llvm_cbe_u = (((unsigned int )(bool )llvm_cbe_t));
...

This fixes a miscompilation of mediabench/adpcm/rawdaudio/rawdaudio and
403.gcc with the CBE, regressions from LLVM 2.2. Tanya, please pull 
this into the release branch.

llvm-svn: 51813
2008-05-31 09:23:55 +00:00
Dan Gohman
00823cb0d4 Teach the DAGISelEmitter to not compute the variable_ops operand
index for the input pattern in terms of the output pattern. Instead
keep track of how many fixed operands the input pattern actually
has, and have the input matching code pass the output-emitting
function that index value. This simplifies the code, disentangles
variables_ops from the support for predication operations, and
makes variable_ops more robust.

llvm-svn: 51808
2008-05-31 02:11:25 +00:00
Evan Cheng
f1fb1d7abf Fix indentation.
llvm-svn: 51792
2008-05-30 22:39:18 +00:00
Bill Wendling
244b4db58d Add the "AsCheapAsAMove" flag to some 64-bit xor instructions.
llvm-svn: 51761
2008-05-30 06:47:04 +00:00
Dan Gohman
aa8fcd5657 Add patterns for CALL32m and CALL64m. They aren't matched in most
cases due to an isel deficiency already noted in
lib/Target/X86/README.txt, but they can be matched in this fold-call.ll
testcase, for example.

This is interesting mainly because it exposes a tricky tblgen bug;
tblgen was incorrectly computing the starting index for variable_ops
in the case of a complex pattern.

llvm-svn: 51706
2008-05-29 21:50:34 +00:00
Bill Wendling
2ba98ca60f Remove more iostream header includes. Needed to implement a "FlushStream"
function to flush a specified std::ostream.

llvm-svn: 51705
2008-05-29 21:46:33 +00:00
Dan Gohman
4e87d82476 Fix a tblgen problem handling variable_ops in tblgen instruction
definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.

This fixes "rdar://5791600", whatever that is ;-).

llvm-svn: 51699
2008-05-29 19:57:41 +00:00
Dan Gohman
e256337a1a Expand small memmovs using inline code. Set the X86 threshold for expanding
memmove to a more plausible value, now that it's actually being used.

llvm-svn: 51696
2008-05-29 19:42:22 +00:00
Evan Cheng
04c0915a2f Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.
llvm-svn: 51667
2008-05-29 08:22:04 +00:00
Bill Wendling
81199f0cc8 XOR?RI instructions aren't as cheap as moves.
llvm-svn: 51664
2008-05-29 03:46:36 +00:00
Bill Wendling
edb38e9410 Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the
like.

llvm-svn: 51662
2008-05-29 01:02:09 +00:00
Bill Wendling
b56bc61cf4 Add a flag to indicate that an instruction is as cheap (or cheaper) than a move
instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.

llvm-svn: 51660
2008-05-28 22:54:52 +00:00