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16 Commits

Author SHA1 Message Date
Chandler Carruth
3e8b3f66be Sort the #include lines for utils/... 
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
 2012-12-04 10:37:14 +00:00
Rafael Espindola
d404d4c18c Fix a build problem with xlc. The error message was 
"../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+".
"../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate.

Patch by Kai.

llvm-svn: 167311
 2012-11-02 20:57:36 +00:00
Joerg Sonnenberger
839f6c1a88 Remove exception handling usage from tblgen. 
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 

llvm-svn: 166712
 2012-10-25 20:33:17 +00:00
Joerg Sonnenberger
8fa017919b Don't use stack unwinding to provide the location information for 
SetTheory, but pass down the location explicitly.

llvm-svn: 166629
 2012-10-24 22:03:59 +00:00
Sean Silva
a6a1c05042 tblgen: Mechanically move dynamic_cast<> to dyn_cast<>. 
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

llvm-svn: 165646
 2012-10-10 20:24:43 +00:00
Andrew Trick
782f561e6a TableGen subtarget emitter cleanup. 
Consistently evaluate Aliases and Sequences recursively.

llvm-svn: 165604
 2012-10-10 05:43:13 +00:00
Andrew Trick
d6d5b63b3b Added instregex support to TableGen subtarget emitter. 
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.

llvm-svn: 165180
 2012-10-03 23:06:32 +00:00
Andrew Trick
00263532fa TableGen subtarget emitter, nearly first class support for SchedAlias. 
A processor can now arbitrarily alias one SchedWrite onto
another. Only the SchedAlias definition need be within the processor
model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or
transitively refer to another alias.

llvm-svn: 165179
 2012-10-03 23:06:28 +00:00
Andrew Trick
35fd7cbe58 Cleanup TableGen subtarget emitter. 
llvm-svn: 165178
 2012-10-03 23:06:25 +00:00
Andrew Trick
7a73f9d7f4 Machine Model (-schedmodel only). Added SchedAliases. 
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.

llvm-svn: 164451
 2012-09-22 02:24:21 +00:00
Andrew Trick
3ed8eed2ed SchedMachineModel: compress the CPU's WriteLatencyTable. 
llvm-svn: 164199
 2012-09-19 04:43:19 +00:00
Andrew Trick
d15e58e200 TableGen subtarget parser: Add getProcResourcesIdx(). 
llvm-svn: 164057
 2012-09-17 22:18:43 +00:00
Andrew Trick
25c8faee30 TableGen subtarget parser. Handle new machine model. 
Collect processor resources from the subtarget defs.

llvm-svn: 163953
 2012-09-15 00:20:02 +00:00
Andrew Trick
0587f1d794 TableGen subtarget parser. Handle new machine model. 
Infer SchedClasses from variants defined by the target or subtarget.

llvm-svn: 163952
 2012-09-15 00:19:59 +00:00
Andrew Trick
b324ff57ad TableGen subtarget parser. Handle new machine model. 
Collect SchedClasses and SchedRW types from the subtarget defs.

llvm-svn: 163951
 2012-09-15 00:19:57 +00:00
Andrew Trick
b9c8074dcd I'm introducing a new machine model to simultaneously allow simple 
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
 2012-07-07 04:00:00 +00:00