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7b7954f53f
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39 Commits

Author SHA1 Message Date
Evan Cheng
7b7954f53f movlps and movlpd should be modeled as two address code. 
llvm-svn: 27221
 2006-03-28 07:01:28 +00:00
Evan Cheng
9f0e244187 Typo 
llvm-svn: 27219
 2006-03-28 06:53:49 +00:00
Evan Cheng
fb4b2bfc7d * Prefer using operation of matching types. e.g unpcklpd rather than movlhps. 
* Bug fixes.

llvm-svn: 27218
 2006-03-28 06:50:32 +00:00
Evan Cheng
4d554dae17 - Clean up / consoladate various shuffle masks. 
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210
 2006-03-28 02:43:26 +00:00
Evan Cheng
d8d7ec47bd Model unpack lower and interleave as vector_shuffle so we can lower the 
intrinsics as such.

llvm-svn: 27200
 2006-03-28 00:39:58 +00:00
Chris Lattner
b64eb6593a unbreak the build 
llvm-svn: 27174
 2006-03-27 16:52:45 +00:00
Evan Cheng
0865274fa5 Use pcmpeq to generate vector of all ones. 
llvm-svn: 27167
 2006-03-27 07:00:16 +00:00
Evan Cheng
1dfbede1d1 Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups 
llvm-svn: 27150
 2006-03-26 09:53:12 +00:00
Evan Cheng
e5807f6b47 Build arbitrary vector with more than 2 distinct scalar elements with a 
series of unpack and interleave ops.

llvm-svn: 27119
 2006-03-25 09:37:23 +00:00
Evan Cheng
8601147e68 Added SSE cachebility ops 
llvm-svn: 27103
 2006-03-25 06:03:26 +00:00
Evan Cheng
234090b386 Added 128-bit packed integer subtraction. 
llvm-svn: 27096
 2006-03-25 01:33:37 +00:00
Evan Cheng
041c9c534b Added CVTSS2SI. 
llvm-svn: 27094
 2006-03-25 01:00:18 +00:00
Evan Cheng
bdb85b387f Support for scalar to vector with zero extension. 
llvm-svn: 27091
 2006-03-24 23:15:12 +00:00
Evan Cheng
33dad39b46 Added LDMXCSR 
llvm-svn: 27087
 2006-03-24 22:28:37 +00:00
Chris Lattner
2d08e8aee1 plug the intrinsics into the patterns for movmsk* 
llvm-svn: 27083
 2006-03-24 21:49:18 +00:00
Evan Cheng
d58d54cf3e Handle BUILD_VECTOR with all zero elements. 
llvm-svn: 27056
 2006-03-24 07:29:27 +00:00
Evan Cheng
3028b04057 More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd. 
llvm-svn: 27040
 2006-03-24 02:58:06 +00:00
Evan Cheng
68410804f0 Handle more shuffle cases with SHUFP* instructions. 
llvm-svn: 27024
 2006-03-24 01:18:28 +00:00
Evan Cheng
a6dc6e535d Following icc's lead: use movdqa to load / store 128-bit integer vectors 
llvm-svn: 26980
 2006-03-23 07:44:07 +00:00
Evan Cheng
c1fe87ea8b Add v4i32 <-> v4f32 bitconvert patterns. 
llvm-svn: 26969
 2006-03-23 02:36:37 +00:00
Evan Cheng
5f7cf963db Add 128-bit integer vector load and add (for testing). 
llvm-svn: 26967
 2006-03-23 01:57:24 +00:00
Evan Cheng
56b67b2c4f SHUFP* are two address code. 
llvm-svn: 26959
 2006-03-22 20:08:18 +00:00
Evan Cheng
ae6a39ea92 - Supposely movlhps is faster / better than unpcklpd. 
- Don't forget pshufd is only available with sse2.

llvm-svn: 26956
 2006-03-22 19:16:21 +00:00
Evan Cheng
cff38e19c3 - Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support 
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.

llvm-svn: 26954
 2006-03-22 18:59:22 +00:00
Evan Cheng
f6dc0a7f5e - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches 
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

llvm-svn: 26951
 2006-03-22 08:01:21 +00:00
Evan Cheng
25440d19b1 Fix PSHUF* and SHUF* jit code emission problems 
llvm-svn: 26949
 2006-03-22 07:10:28 +00:00
Evan Cheng
7aac4350c7 Some splat and shuffle support. 
llvm-svn: 26940
 2006-03-22 02:53:00 +00:00
Evan Cheng
47dd756c72 - Use movaps to store 128-bit vector integers. 
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

llvm-svn: 26932
 2006-03-21 23:01:21 +00:00
Evan Cheng
6ec225863c - Remove scalar to vector pseudo ops. They are just wrong. 
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

llvm-svn: 26919
 2006-03-21 07:09:35 +00:00
Evan Cheng
a4db61ddc1 x86 ISD::SCALAR_TO_VECTOR support. 
llvm-svn: 26911
 2006-03-21 00:33:35 +00:00
Evan Cheng
c63d434203 Move a few things around. 
llvm-svn: 26893
 2006-03-20 06:04:52 +00:00
Evan Cheng
cc1e38c242 Vector undef's 
llvm-svn: 26870
 2006-03-19 09:38:54 +00:00
Evan Cheng
8dd794ea70 Use the generic vector register classes VR64 / VR128 rather than V4F32, 
V8I16, etc.

llvm-svn: 26838
 2006-03-18 01:23:20 +00:00
Evan Cheng
ee1a44d5d8 Move some pattern fragments to the right files. 
llvm-svn: 26831
 2006-03-17 19:55:52 +00:00
Evan Cheng
005de9e2bb Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. 
Fixed some existing bugs (wrong predicates, prefixes) at the same time.

llvm-svn: 26310
 2006-02-22 02:26:30 +00:00
Evan Cheng
8ab6294f94 One more round of reorg so sabre doesn't freak out. :-) 
llvm-svn: 26303
 2006-02-21 20:00:20 +00:00
Evan Cheng
f7296d8fa5 A big more cleaning up. 
llvm-svn: 26302
 2006-02-21 19:30:30 +00:00
Evan Cheng
223d3a073a Moving things to their proper places. 
llvm-svn: 26301
 2006-02-21 19:26:52 +00:00
Evan Cheng
fee17dfff8 Split instruction info into multiple files, one for each of x87, MMX, and SSE. 
llvm-svn: 26300
 2006-02-21 19:13:53 +00:00