Jim Grosbach
608e4fd221
Simplify test file a bit.
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llvm-svn: 116540
2010-10-14 23:32:44 +00:00
Jim Grosbach
26842cb893
Add testcase for RRX and ASRS (which effectively tests MOVs, since those
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are just forms of that instruction).
llvm-svn: 116538
2010-10-14 23:29:18 +00:00
Jim Grosbach
73c78f8790
MOVi16 and MOVT ARM mode encodings.
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llvm-svn: 116498
2010-10-14 18:54:27 +00:00
Jim Grosbach
8f0bea85bf
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
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llvm-svn: 116421
2010-10-13 19:56:10 +00:00
Jim Grosbach
9c4a598ef2
Add ARM mode operand encoding information for ADDE/SUBE instructions.
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llvm-svn: 116412
2010-10-13 18:00:52 +00:00
Jim Grosbach
3fe0337063
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
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arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
Jim Grosbach
0038f2eec6
Be nitpicky and line up the comments.
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llvm-svn: 116365
2010-10-12 23:14:03 +00:00
Jim Grosbach
10d9bbe0ca
Add encoding information for the remainder of the generic arithmetic
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ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
Jim Grosbach
29ef87e765
MC machine encoding for simple aritmetic instructions that use a shifted
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register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
Jim Grosbach
3075d28c15
Implement a few more binary encoding bits. Still very early stage proof-of-
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concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
Jim Grosbach
edbbf33203
Add test file for simple ARM binary encodings with MC
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llvm-svn: 116024
2010-10-08 00:47:59 +00:00