Evan Cheng
7c8d7bc4b3
Didn't mean to check this in. No MMX support yet.
...
llvm-svn: 26933
2006-03-21 23:04:23 +00:00
Evan Cheng
47dd756c72
- Use movaps to store 128-bit vector integers.
...
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
Chris Lattner
31a93c7740
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
...
llvm-svn: 26930
2006-03-21 20:51:05 +00:00
Evan Cheng
a56ed39464
Combine 2 entries
...
llvm-svn: 26921
2006-03-21 07:18:26 +00:00
Evan Cheng
f8d8d45ff8
Add a note about x86 register coallescing
...
llvm-svn: 26920
2006-03-21 07:12:57 +00:00
Evan Cheng
6ec225863c
- Remove scalar to vector pseudo ops. They are just wrong.
...
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
llvm-svn: 26919
2006-03-21 07:09:35 +00:00
Evan Cheng
a4db61ddc1
x86 ISD::SCALAR_TO_VECTOR support.
...
llvm-svn: 26911
2006-03-21 00:33:35 +00:00
Evan Cheng
d90127aafd
Junk unused vector register classes.
...
llvm-svn: 26910
2006-03-21 00:30:59 +00:00
Chris Lattner
09ede9ec9f
Add a build_vector node
...
llvm-svn: 26895
2006-03-20 06:18:01 +00:00
Evan Cheng
c63d434203
Move a few things around.
...
llvm-svn: 26893
2006-03-20 06:04:52 +00:00
Chris Lattner
9a87d3e90d
add a note with a testcase
...
llvm-svn: 26877
2006-03-19 22:27:41 +00:00
Evan Cheng
cc1e38c242
Vector undef's
...
llvm-svn: 26870
2006-03-19 09:38:54 +00:00
Evan Cheng
99327f9351
Turning on LSR by default
...
llvm-svn: 26861
2006-03-19 06:08:49 +00:00
Evan Cheng
98b79bf7ec
Remember which tests are hurt by LSR.
...
llvm-svn: 26860
2006-03-19 06:08:11 +00:00
Chris Lattner
1bd0aaf2b8
rename these nodes
...
llvm-svn: 26848
2006-03-19 01:13:28 +00:00
Evan Cheng
8dd794ea70
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
Evan Cheng
f4774c9091
Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
...
llvm-svn: 26833
2006-03-17 20:31:41 +00:00
Evan Cheng
ee1a44d5d8
Move some pattern fragments to the right files.
...
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
Chris Lattner
647503bccc
Disable x86 fastcc from passing args in registers
...
llvm-svn: 26824
2006-03-17 17:27:47 +00:00
Chris Lattner
a71bc63ced
Parameterize the number of integer arguments to pass in registers
...
llvm-svn: 26818
2006-03-17 05:10:20 +00:00
Evan Cheng
1f5cb60f28
Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
...
llvm-svn: 26817
2006-03-17 02:36:22 +00:00
Evan Cheng
fc79bdafbe
Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
...
ADD32ri8.
llvm-svn: 26816
2006-03-17 02:25:01 +00:00
Evan Cheng
d16fa97974
- Nuke 16-bit SBB instructions. We'll never use them.
...
- Nuke a bogus comment.
llvm-svn: 26815
2006-03-17 02:24:04 +00:00
Nate Begeman
42736d46b2
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
Evan Cheng
33055a8aba
A new entry.
...
llvm-svn: 26810
2006-03-16 22:44:22 +00:00
Evan Cheng
0e1abe6e19
Bug fix: condition inverted.
...
llvm-svn: 26804
2006-03-16 22:02:48 +00:00
Evan Cheng
cad75d9f0c
Added a way for TargetLowering to specify what values can be used as the
...
scale component of the target addressing mode.
llvm-svn: 26802
2006-03-16 21:47:42 +00:00
Evan Cheng
7ec94f2ff7
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
...
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
Evan Cheng
ed013bd937
Add LSR hooks.
...
llvm-svn: 26740
2006-03-13 23:18:16 +00:00
Evan Cheng
471bd00cb5
Add option -enable-x86-lsr to enable x86 loop strength reduction pass.
...
llvm-svn: 26665
2006-03-09 21:51:28 +00:00
Chris Lattner
57acce1443
a couple of miscellaneous things.
...
llvm-svn: 26625
2006-03-09 01:39:46 +00:00
Evan Cheng
d73d06f052
X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag.
...
llvm-svn: 26604
2006-03-07 23:34:23 +00:00
Evan Cheng
a3e0a7f652
Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest.
...
and variable value.
Similarly for memcpy.
llvm-svn: 26603
2006-03-07 23:29:39 +00:00
Jim Laskey
91d5ce2531
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
Evan Cheng
03940bfcfe
- Emit subsections_via_symbols for Darwin.
...
- Conditionalize Dwarf debugging output (Darwin only for now).
llvm-svn: 26582
2006-03-07 02:23:26 +00:00
Evan Cheng
2327759419
Enable Dwarf debugging info.
...
llvm-svn: 26581
2006-03-07 02:02:57 +00:00
Chris Lattner
6b0947c277
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
Chris Lattner
55fbd49ca9
add a note for something evan noticed
...
llvm-svn: 26539
2006-03-05 01:15:18 +00:00
Evan Cheng
65b5c2c680
Add an entry
...
llvm-svn: 26520
2006-03-04 07:49:50 +00:00
Evan Cheng
2b45c57663
MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
...
rep/stos and rep/mov if the count is not a constant. We could do
rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.
Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.
llvm-svn: 26517
2006-03-04 02:48:56 +00:00
Evan Cheng
f2a0107221
Typo
...
llvm-svn: 26512
2006-03-04 01:12:00 +00:00
Chris Lattner
999aa36a04
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
Evan Cheng
ebe1f272b7
Vector op lowering.
...
llvm-svn: 26438
2006-03-01 01:11:20 +00:00
Evan Cheng
e5ae39621b
Another entry.
...
llvm-svn: 26430
2006-02-28 23:38:49 +00:00
Evan Cheng
fab8a53944
Don't match x << 1 to LEAL. It's better to emit x + x.
...
llvm-svn: 26429
2006-02-28 21:13:57 +00:00
Evan Cheng
40a98fd65d
ConstantPoolIndex is now the displacement portion of the address (rather
...
than base).
llvm-svn: 26382
2006-02-26 09:12:34 +00:00
Evan Cheng
a93aa7e4c9
Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
...
and 2005-05-12-Int64ToFP.
llvm-svn: 26380
2006-02-26 08:28:12 +00:00
Evan Cheng
de768027d9
* Cleaned up addressing mode matching code.
...
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
llvm-svn: 26376
2006-02-25 10:09:08 +00:00
Evan Cheng
8a6f03bb0e
Updates.
...
llvm-svn: 26375
2006-02-25 10:04:07 +00:00
Evan Cheng
995c9806ba
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
...
* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
llvm-svn: 26374
2006-02-25 10:02:21 +00:00