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234 Commits

Author SHA1 Message Date
Jay Foad
7d05fea7f8 Remove some unnecessary includes of PseudoSourceValue.h. 
llvm-svn: 144631
 2011-11-15 07:24:32 +00:00
Chad Rosier
4e05d7f12c Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

llvm-svn: 144585
 2011-11-14 23:04:09 +00:00
Chad Rosier
48b92815e0 Add support for inlining small memcpys. 
rdar://10412592

llvm-svn: 144578
 2011-11-14 22:46:17 +00:00
Chad Rosier
8aa8f14940 Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.

llvm-svn: 144576
 2011-11-14 22:34:48 +00:00
Chad Rosier
65395ac4d0 Add support for Thumb load/stores with negative offsets. 
rdar://10412592

llvm-svn: 144565
 2011-11-14 20:22:27 +00:00
Chad Rosier
0e5094ca87 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592

llvm-svn: 144518
 2011-11-14 04:09:28 +00:00
Chad Rosier
58ab241006 The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
llvm-svn: 144494
 2011-11-13 09:44:21 +00:00
Chad Rosier
8cfccc356e Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
llvm-svn: 144492
 2011-11-13 05:14:43 +00:00
Chad Rosier
0770c4834a Fix comments. 
llvm-svn: 144490
 2011-11-13 04:25:02 +00:00
Chad Rosier
acd199b5a4 Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

llvm-svn: 144488
 2011-11-13 02:23:59 +00:00
Chad Rosier
a2a0fbeded Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
llvm-svn: 144426
 2011-11-11 23:31:03 +00:00
Chad Rosier
98f48b009e Rename variables to avoid confusion. No functionallity change intended. 
llvm-svn: 144377
 2011-11-11 06:27:41 +00:00
Chad Rosier
feb72bfc08 Add support for using immediates with select instructions. 
rdar://10412592

llvm-svn: 144376
 2011-11-11 06:20:39 +00:00
Chad Rosier
38f07d3f9c When loading a value, treat an i1 as an i8. 
llvm-svn: 144356
 2011-11-11 02:38:59 +00:00
Chad Rosier
ac92994773 Add support for using MVN to materialize negative constants. 
rdar://10412592

llvm-svn: 144348
 2011-11-11 00:36:21 +00:00
Chad Rosier
7b7dced006 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

llvm-svn: 144316
 2011-11-10 21:09:49 +00:00
Chad Rosier
69cdae5eb9 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
 2011-11-10 01:30:39 +00:00
Chad Rosier
f47b941510 The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. 
rdar://10418009

llvm-svn: 144213
 2011-11-09 21:30:12 +00:00
Chad Rosier
e32fed6868 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592

llvm-svn: 144163
 2011-11-09 03:22:02 +00:00
Chad Rosier
24a6e399f8 ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. 
No functional change intended.

llvm-svn: 144122
 2011-11-08 21:12:00 +00:00
Chad Rosier
4b12a5b7fc Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
 2011-11-08 00:03:32 +00:00
Chad Rosier
806ffd8918 Add support for passing i1, i8, and i16 call parameters. Also, be sure to 
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.

llvm-svn: 143821
 2011-11-05 20:16:15 +00:00
Chad Rosier
5e54485e51 Cannot create a result register for non-legal types. 
llvm-svn: 143749
 2011-11-04 23:45:39 +00:00
Chad Rosier
a900a3e2f6 When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit 
in a 16-bit immediate.  However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend.  This prevents us from materializing things
such as 'true' (i.e., i1 1).

llvm-svn: 143743
 2011-11-04 23:09:49 +00:00
Chad Rosier
0143eb6f22 Enable support for materializing i1, i8, and i16 integers via move immediate. 
llvm-svn: 143739
 2011-11-04 22:29:00 +00:00
Chad Rosier
8836fe3bbd Indentation. 
llvm-svn: 143670
 2011-11-04 00:58:10 +00:00
Chad Rosier
21cd759234 Add fast-isel support for returning i1, i8, and i16. 
llvm-svn: 143669
 2011-11-04 00:50:21 +00:00
Chad Rosier
74c4e2c2d9 Add support for sign-extending non-legal types in SelectSIToFP(). 
llvm-svn: 143603
 2011-11-03 02:04:59 +00:00
Chad Rosier
8a613c5ec5 Add support for comparing integer non-legal types. 
llvm-svn: 143559
 2011-11-02 18:08:25 +00:00
Chad Rosier
e94ff7c26e Factor out an EmitIntExt function. No functionality change intended. 
llvm-svn: 143547
 2011-11-02 17:20:24 +00:00
Chad Rosier
f72870096b Factor out a SelectTrunc function. No functionality change intended. 
llvm-svn: 143523
 2011-11-02 00:18:48 +00:00
Chad Rosier
e76ba1b654 A branch predicated on a constant can just FastEmit an unconditional branch. 
llvm-svn: 143086
 2011-10-27 00:21:16 +00:00
Chad Rosier
e3141f4f8b Add a TODO comment. FastISel works by parsing each basic block from the bottom 
up.  Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle.  This creates many more 
opportunities for target specific fast-isel.

llvm-svn: 143079
 2011-10-26 23:34:37 +00:00
Chad Rosier
75378507e3 Factor a little more code into EmitCmp, which should have been done in the first 
place.  No functional change intended.

llvm-svn: 143078
 2011-10-26 23:25:44 +00:00
Chad Rosier
52109646da Use EmitCmp in SelectBranch. No functional change intended. 
llvm-svn: 143076
 2011-10-26 23:17:28 +00:00
Chad Rosier
3f38cb48de Factor out an EmitCmp function that can be used by both SelectCmp and 
SelectBranch.  No functional change intended.

llvm-svn: 143072
 2011-10-26 22:47:55 +00:00
Chad Rosier
ef5ee1892c Add a few FIXME comments. 
llvm-svn: 142299
 2011-10-17 22:54:23 +00:00
Bill Wendling
1d585d7961 Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.

llvm-svn: 140936
 2011-10-01 08:00:54 +00:00
Jim Grosbach
d94ffffc87 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Jim Grosbach
74f96e7f3c Tidy up a few 80 column violations. 
llvm-svn: 139636
 2011-09-13 20:30:37 +00:00
Eli Friedman
383a3c76b2 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Chad Rosier
aa490636db Fixup for functions that return a bool. 
llvm-svn: 138918
 2011-08-31 23:49:05 +00:00
Jim Grosbach
3832c5ac34 [SU]XT[BH] are only available on ARMv6 and up. 
llvm-svn: 138373
 2011-08-23 20:53:08 +00:00
Jim Grosbach
7098677dbc ARM extend instructions simplification. 
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.

llvm-svn: 136225
 2011-07-27 16:47:19 +00:00
Evan Cheng
bff5f78cb5 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. 
llvm-svn: 135636
 2011-07-20 23:34:39 +00:00
Chris Lattner
e1fe7061ce land David Blaikie's patch to de-constify Type, with a few tweaks. 
llvm-svn: 135375
 2011-07-18 04:54:35 +00:00
Evan Cheng
65e7766262 Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. 
llvm-svn: 134030
 2011-06-28 21:14:33 +00:00
Evan Cheng
4a169be530 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
 2011-06-28 19:10:37 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Eli Friedman
eae10d6163 Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. 
rdar://9431157

llvm-svn: 132522
 2011-06-03 01:13:19 +00:00