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138396 Commits

Author SHA1 Message Date
Quentin Colombet
b578cb62bb [RegisterBankInfo] Avoid heap allocation in most cases.
The OperandsMapper class is used heavy in RegBankSelect and each
instantiation triggered a heap allocation for the array of operands.
Instead, use a SmallVector with a big enough size such that most of the
cases do not have to use dynamically allocated memory.

This improves the compile time of the RegBankSelect pass.

llvm-svn: 281916
2016-09-19 17:33:55 +00:00
Matthias Braun
c02cdc0d60 LiveRangeCalc: Fix reporting of invalid vreg usage in liveness calculation
Machine programs need a definition of each vreg before reaching a use
(the definition may come from an IMPLICIT_DEF instruction). This class
of errors is not detected by the MachineVerifier because of efficiency
concerns. LiveRangeCalc used to report these problems, make it do that
again (followup to r279625).

Also use report_fatal_error() instead of llvm_unreachable() as the error
reporting is only present in asserts build anyway.

llvm-svn: 281914
2016-09-19 16:49:45 +00:00
Dehao Chen
4d399f0ac6 Only set branch weight during sample pgo annotation when max_weight of the branch is non-zero. Otherwise use default static profile to set branch probability.
Summary: It does not make sense to set equal weights for all unkown branches as we have static branch prediction available.

Reviewers: dnovillo

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24732

llvm-svn: 281912
2016-09-19 16:33:41 +00:00
Dehao Chen
302fe385af Use call target count to derive the call instruction weight
Summary: The call target count profile is directly derived from LBR branch->target data. This is more reliable than instruction frequency profiles that could be moved across basic block boundaries. This patches uses call target count profile to annotate call instructions.

Reviewers: davidxl, dnovillo

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24410

llvm-svn: 281911
2016-09-19 16:06:37 +00:00
Etienne Bergeron
6822e52e5d [asan] Support dynamic shadow address instrumentation
Summary:
This patch is adding the support for a shadow memory with
dynamically allocated address range.

The compiler-rt needs to export a symbol containing the shadow
memory range.

This is required to support ASAN on windows 64-bits.

Reviewers: kcc, rnk, vitalybuka

Subscribers: kubabrecka, dberris, llvm-commits, chrisha

Differential Revision: https://reviews.llvm.org/D23354

llvm-svn: 281908
2016-09-19 15:58:38 +00:00
Zachary Turner
d6c1a8aec3 [Support] Add StringRef::withNullAsEmpty()
When porting large bodies of code from using const char*
to StringRef, it is helpful to be able to treat nullptr
as an empty string, since that it is often what it is used
to indicate in C-style code.

Differential Revision: https://reviews.llvm.org/D24697

llvm-svn: 281906
2016-09-19 15:34:51 +00:00
Nico Weber
99a8836600 Revert r281841, it does not work on Windows (PR30443).
llvm-svn: 281905
2016-09-19 15:22:04 +00:00
Valery Pykhtin
9c39968ce1 [AMDGPU] Refactor VOPC instruction TD definitions
Differential Revision: https://reviews.llvm.org/D24546

llvm-svn: 281903
2016-09-19 14:39:49 +00:00
Diana Picus
0020aa4a64 [AArch64] Fix encoding for lsl #12 in add/sub immediates
Whenever an add/sub immediate needs a fixup, we set that immediate field to zero,
which is correct, but we also set the shift bits to zero, which is not true for
instructions that use lsl #12. This patch makes sure that if lsl #12 was used,
it will appear in the encoding of the instruction.

Differential Revision: https://reviews.llvm.org/D23930

llvm-svn: 281898
2016-09-19 11:10:18 +00:00
Sam Kolton
dc0750f4ac [AMDGPU] Fix s_branch with -1 offset
Summary:
In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0.
'''
label:
    s_branch label  // should emit [0xff,0xff,0x82,0xbf]
'''

Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result.

Reviewers: vpykhtin, artem.tamazov, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl

Differential Revision: https://reviews.llvm.org/D24671

llvm-svn: 281896
2016-09-19 10:20:55 +00:00
Keith Walker
64915fd385 Add @llvm.dbg.value entries for the phi node created by -mem2reg
When phi nodes are created in the -mem2reg phase, the @llvm.dbg.declare
entries are converted to @llvm.dbg.value entries at the place where the
store instructions existed. However no entry is created to describe
the resulting value of the phi node.

The effect of this is especially noticeable in for loops which have a
constant for the intial value; the loop control variable's location
would be described as the intial constant value in the loop body once
the -mem2reg optimization phase was run.

This change adds the creation of the @llvm.dbg.value entries to describe
variables whose location is the result of a phi node created in -mem2reg.

Also when the phi node is finally lowered to a machine instruction it
is important that the lowered "load" instruction is placed before the
associated DEBUG_VALUE entry describing the value loaded.

Differential Revision: https://reviews.llvm.org/D23715

llvm-svn: 281895
2016-09-19 09:49:30 +00:00
Oliver Stannard
07a1bb0354 [Thumb] Set correct initial mapping symbol for big-endian thumb
The initial mapping symbol state is set from the triple, but we only checked
for the little-endian thumb triple, so could end up with an ARM mapping symbol
for big-endian thumb.

Differential Revision: https://reviews.llvm.org/D24553

llvm-svn: 281894
2016-09-19 09:21:45 +00:00
Tim Northover
11b2b57958 ARM: check alignment before transforming ldr -> ldm (or similar).
ldm and stm instructions always require 4-byte alignment on the pointer, but we
weren't checking this before trying to reduce code-size by replacing a
post-indexed load/store with them. Unfortunately, we were also dropping this
incormation in DAG ISel too, but that's easy enough to fix.

llvm-svn: 281893
2016-09-19 09:11:09 +00:00
Elena Demikhovsky
53520a83c1 [X86 Codegen Test] Divided masked_memop into several files. NFC.
The masked_memop.ll became huge. I extracted AVX-512 specific tests into separate files.

llvm-svn: 281892
2016-09-19 08:58:43 +00:00
James Molloy
1f17c2f83a [SimplifyCFG] Update (AND) IR flags when CSE'ing instructions
We were updating metadata but not IR flags. Because we pick an arbitrary instruction to be the CSE candidate, it comes down to luck (50% or less chance) if this results in broken codegen or not, which is why PR30373 which is actually not the fault of the commit it was bisected down to.

Fixes PR30373.

llvm-svn: 281889
2016-09-19 08:23:08 +00:00
Craig Topper
c7f779bf05 [X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when the input is not the output of an instruction.
SUBREG_TO_REG is supposed to indicate that the super register has been zeroed, but we can't prove that if we don't know where it came from.

llvm-svn: 281885
2016-09-19 02:53:43 +00:00
Craig Topper
9f5d417d08 [AVX-512] Add support for lowering fp_to_f16 and f16_to_fp when VLX is supported regardless of whether F16C is also supported.
Still need to add support for lowering using AVX512F when neither VLX or F16C is supported.

llvm-svn: 281884
2016-09-19 02:53:37 +00:00
Vedant Kumar
0b4b017d99 [llvm-cov] Emit a link to some documentation
llvm-svn: 281883
2016-09-19 02:15:59 +00:00
Vedant Kumar
f64114d9a8 [llvm-cov] Delete the NonCodeLines field, it was always dead
llvm-svn: 281882
2016-09-19 01:46:01 +00:00
Dean Michael Berris
fca2ef5fb0 [XRay] ARM 32-bit no-Thumb support in LLVM
This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter.
This is one of 3 commits to different repositories of XRay ARM port. The other 2 are:

https://reviews.llvm.org/D23932 (Clang test)
https://reviews.llvm.org/D23933 (compiler-rt)

Differential Revision: https://reviews.llvm.org/D23931

llvm-svn: 281878
2016-09-19 00:54:35 +00:00
Vedant Kumar
8dc1a14b03 [llvm-cov] Teach the coverage exporter about instantiation coverage
While we're at it, re-use the logic from CoverageReport to compute
summaries.

llvm-svn: 281877
2016-09-19 00:38:29 +00:00
Vedant Kumar
6768ede0e0 [llvm-cov] Make a helper method static for re-use (NFC)
llvm-svn: 281876
2016-09-19 00:38:25 +00:00
Vedant Kumar
2eca4b6e3f [llvm-cov] Track function and instantiation coverage separately
These are distinct statistics which are useful to look at separately.

Example: say you have a template function "foo" with 5 instantiations
and only 3 of them are covered. Then this contributes (1/1) to the total
function coverage and (3/5) to the total instantiation coverage. I.e,
the old "Function Coverage" column has been renamed to "Instantiation
Coverage", and the new "Function Coverage" aggregates information from
the various instantiations of a function.

One benefit of making this switch is that the Line and Region coverage
columns will start making sense. Let's continue the example and assume
that the 5 instantiations of "foo" cover {2, 4, 6, 8, 10} out of 10
lines respectively. The new line coverage for "foo" is (10/10), not
(30/50).  The old scenario got confusing because we'd report that there
were more lines in a file than what was actually possible.

llvm-svn: 281875
2016-09-19 00:38:23 +00:00
Vedant Kumar
f4d70a9a8f [llvm-cov] Don't recompute the 'Covered' field from *CoverageInfo (NFC)
llvm-svn: 281874
2016-09-19 00:38:18 +00:00
Vedant Kumar
e723e6ad9c [llvm-cov] Make 'adjustColumnWidths' do less work
This drops some redundant calls to get{UniqueSourceFiles,
CoveredFunctions}. We can figure out the right column widths without
re-doing this expensive work.

This isn't NFC, but I don't want to check in another binary *.covmapping
file with long filenames in it. I tested this locally on a project with
some long filenames (FileCheck).

llvm-svn: 281873
2016-09-19 00:38:16 +00:00
Vedant Kumar
c6a118fd20 [llvm-cov] Drop another redundant 'No.' suffix
llvm-svn: 281872
2016-09-19 00:38:14 +00:00
Vedant Kumar
36110a2aff [utils] Delete the 'check-coverage-regressions' script
In practice, it's way too noisy.

It's also a maintenance burden, since we apparently can't add tests for
it without breaking some Windows setups (see: D22692).

llvm-svn: 281871
2016-09-19 00:38:11 +00:00
Dehao Chen
0a9a8c9c72 Handle Invoke during sample profiler annotation: make it inlinable.
Summary: Previously we reline on inst-combine to remove inlinable invoke instructions. This causes trouble because a few extra optimizations are schedule early that could introduce too much CFG change (e.g. simplifycfg removes too much control flow). This patch handles invoke instruction in-place during sample profile annotation, so that we do not rely on instcombine to remove those invoke instructions.

Reviewers: davidxl, dnovillo

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24409

llvm-svn: 281870
2016-09-18 23:11:37 +00:00
Xinliang David Li
8ab1a937f7 Extend title underline
llvm-svn: 281869
2016-09-18 22:10:19 +00:00
Craig Topper
8173f1a5ca [AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision.
Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future.

llvm-svn: 281868
2016-09-18 21:49:32 +00:00
Craig Topper
040e018f7c [AVX-512] Stop lowering avx512_mask_sqrt intrinsics to ISD:FSQRT with a second operand containing an X86 specific rounding mode encoding that doesn't belong.
llvm-svn: 281867
2016-09-18 21:49:28 +00:00
Kostya Serebryany
637985cabd [libFuzzer] add -print_coverage=1 flag to print coverage directly from libFuzzer
llvm-svn: 281866
2016-09-18 21:47:08 +00:00
Simon Pilgrim
28ff0c8578 Fix covered-switch-default warning
llvm-svn: 281865
2016-09-18 21:08:35 +00:00
Simon Pilgrim
38157a81bd [CostModel][X86] Added scalar float op costs
llvm-svn: 281864
2016-09-18 21:01:20 +00:00
Simon Pilgrim
4d76cedc40 Rename tests
llvm-svn: 281863
2016-09-18 20:25:41 +00:00
Craig Topper
c385adca9d [X86] Fix typo in comment. NFC
llvm-svn: 281862
2016-09-18 18:59:38 +00:00
Craig Topper
b166011773 [AVX-512] Add memory load patterns for the legacy SSE scalar fp to integer conversion intrinsics to be consistent across all intruction sets.
llvm-svn: 281861
2016-09-18 18:59:36 +00:00
Craig Topper
fca6198042 [AVX-512] Remove COPY_TO_REGCLASS from a few patterns that already had the correct register class.
llvm-svn: 281860
2016-09-18 18:59:33 +00:00
Xinliang David Li
ca3730b14d Fix built bot failure
llvm-svn: 281859
2016-09-18 18:52:08 +00:00
Xinliang David Li
3da3a5fee4 [Profile] Implement select instruction instrumentation in IR PGO
Differential Revision: http://reviews.llvm.org/D23727

llvm-svn: 281858
2016-09-18 18:34:07 +00:00
Elena Demikhovsky
fdf2d14b30 [Loop Vectorizer] Consecutive memory access - fixed and simplified
Amended consecutive memory access detection in Loop Vectorizer.
Load/Store were not handled properly without preceding GEP instruction.

Differential Revision: https://reviews.llvm.org/D20789

llvm-svn: 281853
2016-09-18 13:56:08 +00:00
Simon Pilgrim
b15b82c418 [X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp
With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations.

This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware).

While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions.

Differential Revision: https://reviews.llvm.org/D24343

llvm-svn: 281852
2016-09-18 12:45:23 +00:00
Elena Demikhovsky
6f58841f3b [Loop vectorizer] Simplified GEP cloning. NFC.
Simplified GEP cloning in vectorizeMemoryInstruction().
Added an assertion that checks consecutive GEP, which should have only one loop-variant operand.

Differential Revision: https://reviews.llvm.org/D24557

llvm-svn: 281851
2016-09-18 09:22:54 +00:00
Wei Mi
4f31f47bed Change the order of the splitted store from high - low to low - high.
It is a trivial change which could make the testcase easier to be reused
for the store splitting in CodeGenPrepare.

llvm-svn: 281846
2016-09-18 06:10:32 +00:00
Kostya Serebryany
ad93add26c [libFuzzer] use 'if guard' instead of 'if guard >= 0' with trace-pc; change the guard type to intptr_t; use separate array for 8-bit counters
llvm-svn: 281845
2016-09-18 04:52:23 +00:00
Davide Italiano
1b427679af [llvm-objump] Simplify the code. NFCI.
llvm-svn: 281844
2016-09-18 04:39:15 +00:00
Davide Italiano
5be981977a [lib/LTO] Try harder to reduce code duplication. NFCI.
llvm-svn: 281843
2016-09-17 22:32:42 +00:00
Simon Pilgrim
02f84f8e9d [X86][SSE] Added vector udiv combine tests
llvm-svn: 281842
2016-09-17 22:02:23 +00:00
Simon Pilgrim
08eae71db6 [X86][SSE] Added vector fcopysign combine tests
Also demonstrating the poor lowering of fcopysign...

llvm-svn: 281841
2016-09-17 21:31:34 +00:00
Teresa Johnson
8d9ed1ced3 [ThinLTO] Ensure anonymous globals renamed even at -O0
Summary:
This fixes an issue when files are compiled with -flto=thin
at default -O0. We need to rename anonymous globals before attempting
to write the module summary because all values need names for
the summary. This was happening at -O1 and above, but not before
the early exit when constructing the pipeline for -O0.

Also add an internal -prepare-for-thinlto option to enable this
to be tested via opt.

Fixes PR30419.

Reviewers: mehdi_amini

Subscribers: probinson, llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D24701

llvm-svn: 281840
2016-09-17 20:40:16 +00:00