1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-30 07:22:55 +01:00
Commit Graph

104905 Commits

Author SHA1 Message Date
Arnold Schwaighofer
7e23314405 GVN: Preserve invariant.load metadata
If both instructions to be replaced are marked invariant the resulting
instruction is invariant.

rdar://13358910

Fix by Erik Eckstein!

llvm-svn: 211801
2014-06-26 19:51:19 +00:00
Eric Christopher
04713c650c Remove extraneous includes from the target machines.
llvm-svn: 211800
2014-06-26 19:30:05 +00:00
Eric Christopher
da2b8b72dd Move all of the ARM subtarget features down onto the subtarget
rather than the target machine.

llvm-svn: 211799
2014-06-26 19:30:02 +00:00
Eric Christopher
1272c4e1c4 Move the frame lowering constructors out of line to avoid circular
includes.

llvm-svn: 211798
2014-06-26 19:29:59 +00:00
Sanjay Patel
7a41a5b1f1 Changed Phab 'CC' to 'subscriber'; fixed typo
llvm-svn: 211793
2014-06-26 18:12:42 +00:00
Matt Arsenault
c2d6bb970a R600/SI: Add FP mode bits to binary.
The default rounding mode to initialize the mode register needs
to be reported to the runtime. Fill in other bits a kernel
may be interested in setting for future use.

llvm-svn: 211791
2014-06-26 17:22:30 +00:00
Aaron Ballman
a5cd4afa00 Silencing a warning about isZExtFree hiding an inherited virtual function. No functional change intended.
llvm-svn: 211783
2014-06-26 13:45:47 +00:00
Andrea Di Biagio
d30e61d81e Silence a warning due to a comparison between signed and unsigned.
No functional change intended.

llvm-svn: 211782
2014-06-26 13:41:10 +00:00
Will Schmidt
f6e2b6e4f5 Add support for ppc64/power8 as a host
llvm-svn: 211781
2014-06-26 13:37:03 +00:00
Will Schmidt
fbbc998175 add ppc64/pwr8 as target
includes handling DIR_PWR8 where appropriate
The P7Model Itinerary is currently tied in for use under the P8Model, and will be updated later.

llvm-svn: 211779
2014-06-26 13:36:19 +00:00
Renato Golin
9ca48ec4d1 Added parsing co-processor names starting with "cr"
Additional compliant GAS names for coprocessor register name
are enabled for all instruction with parameter MCK_CoprocReg:
LDC,LDC2,STC,STC2,CDP,CDP2,MCR,MCR2,MCRR,MCRR2,MRC,MRC2,MRRC,MRRC2

Patch by Andrey Kuharev.

llvm-svn: 211776
2014-06-26 13:10:53 +00:00
Andrea Di Biagio
3be8532e69 [X86] Improve the selection of SSE3/AVX addsub instructions.
This patch teaches the backend how to canonicalize a shuffle vectors
according to the rule:

 - (shuffle (FADD A, B), (FSUB A, B), Mask) ->
       (shuffle (FSUB A, -B), (FADD A, -B), Mask)

Where 'Mask' is:
  <0,5,2,7>            ;; for v4f32 and v4f64 shuffles.
  <0,3>                ;; for v2f64 shuffles.
  <0,9,2,11,4,13,6,15> ;; for v8f32 shuffles.

In general, ISel only knows how to pattern-match a canonical
'fadd + fsub + blendi' dag node sequence into an ADDSUB instruction.

This new rule allows to convert a non-canonical dag sequence into a
canonical one that will be matched by a single ADDSUB at ISel stage.

The idea of converting a non-canonical ADDSUB into a canonical one by
swapping the first two operands of the shuffle, and then negating the
second operand of the FADD and FSUB, was originally proposed by Hal Finkel.

llvm-svn: 211771
2014-06-26 10:45:21 +00:00
Dinesh Dwivedi
9d122cf780 This patch removed duplicate code for matching patterns
which are now handled in SimplifyUsingDistributiveLaws() 
(after r211261)

Differential Revision: http://reviews.llvm.org/D4253

llvm-svn: 211768
2014-06-26 08:57:33 +00:00
Dinesh Dwivedi
b98a2e9f49 Added instruction combine to transform few more negative values addition to subtraction (Part 2)
This patch enables transforms for

(x + (~(y | c) + 1)   -->   x - (y | c) if c is even

Differential Revision: http://reviews.llvm.org/D4209

llvm-svn: 211765
2014-06-26 05:40:22 +00:00
David Majnemer
96d60954b8 GlobalOpt: Don't optimize thread_local for initializers
Folding a reference to a thread_local variable into another global
variable's initializer is very problematic, there is no relocation that
exists to represent such an access.

llvm-svn: 211762
2014-06-26 03:02:19 +00:00
Matt Arsenault
435a7c1256 R600: Fix vector FMA
llvm-svn: 211757
2014-06-26 01:28:05 +00:00
Reid Kleckner
51475f5aaa Remove forward decl of SmallVectorImpl now that we have the header
Follow up to r211749.

llvm-svn: 211754
2014-06-26 01:03:20 +00:00
Hans Wennborg
0b74da6314 Don't build switch tables for dllimport and TLS variables in GEPs
This is a follow-up to r211331, which failed to notice that we were
returning early from ValidLookupTableConstant for GEPs.

llvm-svn: 211753
2014-06-26 00:30:52 +00:00
Alp Toker
5ad6808be1 MSVC build fix following r211749
Avoid strndup()

llvm-svn: 211752
2014-06-26 00:25:41 +00:00
Adam Nemet
aa04918ad4 [X86] AVX512: Fix asm syntax for packed vcmp
The *_alt defs for vcmp are used by the InstParser (the asm string in the main
def is used by the InstPrinter) .  The former was accepting vector registers
as destination rather than mask registers.

llvm-svn: 211750
2014-06-26 00:21:12 +00:00
Alp Toker
fd9ead3b6f Introduce a string_ostream string builder facilty
string_ostream is a safe and efficient string builder that combines opaque
stack storage with a built-in ostream interface.

small_string_ostream<bytes> additionally permits an explicit stack storage size
other than the default 128 bytes to be provided. Beyond that, storage is
transferred to the heap.

This convenient class can be used in most places an
std::string+raw_string_ostream pair or SmallString<>+raw_svector_ostream pair
would previously have been used, in order to guarantee consistent access
without byte truncation.

The patch also converts much of LLVM to use the new facility. These changes
include several probable bug fixes for truncated output, a programming error
that's no longer possible with the new interface.

llvm-svn: 211749
2014-06-26 00:00:48 +00:00
Argyrios Kyrtzidis
2cce248daa For CrashRecoveryContext::RunSafelyOnThread, propagate Darwin's PRIO_DARWIN_BG to the new thread if it is
set on the calling thread.

This allows libclang's indexing threads to propagate their priority to the clang module building threads.

rdar://17459872

llvm-svn: 211747
2014-06-25 23:54:50 +00:00
Michael Liao
59e5675511 Fix typo
llvm-svn: 211744
2014-06-25 23:39:08 +00:00
Juergen Ributzka
97839af0ec [FastISel][X86] More refactoring of select lowering and XALU folding. NFC.
llvm-svn: 211740
2014-06-25 22:50:59 +00:00
Eric Christopher
ce17f76f37 The includes were sorted. Revert r210578.
llvm-svn: 211737
2014-06-25 22:36:37 +00:00
Juergen Ributzka
70d663743e [FastISel][X86] Refactor XALU folding. NFC.
llvm-svn: 211735
2014-06-25 22:17:23 +00:00
Reid Kleckner
61dbe2c67b Mention that Phabricator users should subscribe to *-commits
This probably explains why a lot of messages get lost for first time
Phabricator users.

llvm-svn: 211731
2014-06-25 20:25:21 +00:00
Juergen Ributzka
87fbbdf13d [FastISel][X86] Only fold the cmp into the select when both instructions are in the same basic block.
If the cmp is in a different basic block, then it is possible that not all
operands of that compare have defined registers. This can happen when one of
the operands to the cmp is a load and the load gets folded into the cmp. In
this case FastISel will skip the load instruction and the vreg is never
defined.

llvm-svn: 211730
2014-06-25 20:06:12 +00:00
Rafael Espindola
9eb4161123 Merge the used symbol scanning of MCObjectStreamer and RecordStreamer.
This completes the refactoring of RecordStreamer.

llvm-svn: 211727
2014-06-25 18:37:33 +00:00
David Blaikie
ac824331fd Revert "PR20038: DebugInfo: Inlined call sites where the caller has debug info but the call itself has no debug location."
This reverts commit r211723.

Breaks the ASan/compiler-rt build... guess I didn't test very far at all
:/.

llvm-svn: 211724
2014-06-25 18:20:54 +00:00
David Blaikie
59345c0fdc PR20038: DebugInfo: Inlined call sites where the caller has debug info but the call itself has no debug location.
This situation does bad things when inlined, so I've fixed Clang not to
produce inlinable call sites without locations when the caller has debug
info (in the one case where I could find that this occurred). This
updates the PR20038 test case to be what clang now produces, and readds
the assertion that had to be removed due to this bug.

I've also beefed up the debug info verifier to help diagnose these
issues in the future, and I hope to add checks to the inliner to just
assert-fail if it encounters this situation. If, in the future, we
decide we have to cope with this situation, the right thing to do is
probably to just remove all the DebugLocs from the inlined instructions.

llvm-svn: 211723
2014-06-25 18:03:10 +00:00
Tyler Nowicki
feb5a3355b Add Rpass-missed and Rpass-analysis reports to the loop vectorizer. The remarks give the vector width of vectorized loops and a brief analysis of loops that fail to be vectorized. For example, an analysis will be generated for loops containing control flow that cannot be simplified to a select. The optimization remarks also give the debug location of expressions that cannot be vectorized, for example the location of an unvectorizable call.
Reviewed by: Arnold Schwaighofer

llvm-svn: 211721
2014-06-25 17:50:15 +00:00
Andrea Di Biagio
de7985179f [X86] Always prefer to lower a VECTOR_SHUFFLE into a BLENDI instead of SHUFP (or VPERM2X128).
This patch teaches method 'LowerVECTOR_SHUFFLE' to give higher precedence to
the check for 'isBlendMask'; the idea is that, when possible, we should firstly
check if a shuffle performs a blend, and in case, try to lower it into a BLENDI
instead of selecting a SHUFP or (worse) a VPERM2X128.

In general:
 - AVX VBLENDPS/D always have better latency and throughput than VPERM2F128;
 - BLENDPS/D instructions tend to always have better 'reciprocal throughput'
   than the equivalent SHUFPS/D;
 - Both BLENDPS/D and SHUFPS/D are often decoded into the same number of
   m-ops; however, a m-op obtained from a BLENDPS/D can be scheduled to more
   than one execution port.

This patch:
 - Moves the check for 'isBlendMask' immediately before the check for
   'isSHUFPMask' within method 'LowerVECTOR_SHUFFLE';
 - Updates existing tests for sse/avx shuffle/blend instructions to verify
   that we select (v)blendps/d when possible (instead of (v)shufps/d or
   vperm2f128).

llvm-svn: 211720
2014-06-25 17:41:58 +00:00
Juergen Ributzka
15c30a5d46 Fix indentation.
llvm-svn: 211717
2014-06-25 16:49:37 +00:00
Rafael Espindola
4cfe49663b Fix the build.
llvm-svn: 211715
2014-06-25 15:47:36 +00:00
Rafael Espindola
196881cf29 Move expression visitation logic up to MCStreamer.
Remove the duplicate from MCRecordStreamer. No functionality change.

llvm-svn: 211714
2014-06-25 15:45:33 +00:00
Eli Bendersky
90bda3bffd Add some test files for r211710.
llvm-svn: 211711
2014-06-25 15:41:39 +00:00
Eli Bendersky
def2619060 Rename loop unrolling and loop vectorizer metadata to have a common prefix.
[LLVM part]

These patches rename the loop unrolling and loop vectorizer metadata
such that they have a common 'llvm.loop.' prefix.  Metadata name
changes:

llvm.vectorizer.* => llvm.loop.vectorizer.*
llvm.loopunroll.* => llvm.loop.unroll.*

This was a suggestion from an earlier review
(http://reviews.llvm.org/D4090) which added the loop unrolling
metadata. 

Patch by Mark Heffernan.

llvm-svn: 211710
2014-06-25 15:41:00 +00:00
JF Bastien
00d9135fdd Fix = delete in MSVC build from r211705
MSVC doesn't support = delete yet, use LLVM_DELETED_FUNCTION instead.

Related to: http://reviews.llvm.org/D3390

llvm-svn: 211709
2014-06-25 15:38:02 +00:00
Rafael Espindola
0e71694bfa Simplify the visitation of target expressions. No functionality change.
llvm-svn: 211707
2014-06-25 15:29:54 +00:00
JF Bastien
80d81f27d3 Random Number Generator (llvm)
Provides an abstraction for a random number generator (RNG) that produces a stream of pseudo-random numbers.
The current implementation uses C++11 facilities and is therefore not cryptographically secure.

The RNG is salted with the text of the current command line invocation.
In addition, a user may specify a seed (reproducible builds).

In clang, the seed can be set via

-frandom-seed=X
In the back end, the seed can be set via

-rng-seed=X
This is the llvm part of the patch.
clang part: D3391

URL: http://reviews.llvm.org/D3390
Author: yln

I'm landing this for the second time, it broke Windows bots the first time around.

llvm-svn: 211705
2014-06-25 15:21:42 +00:00
Rafael Espindola
d7f079b49c Simplify AddValueSymbols. No functionality change.
llvm-svn: 211701
2014-06-25 14:42:14 +00:00
Evgeniy Stepanov
cda29aab74 [msan] Fix bad interaction between with-calls mode and chained origin tracking.
Origin history should only be recorded for uninitialized values, because it is
meaningless otherwise. This change moves __msan_chain_origin to the runtime
library side and makes it conditional on the corresponding shadow value.

Previous code was correct, but _very_ inefficient.

llvm-svn: 211700
2014-06-25 14:41:57 +00:00
Rafael Espindola
6eca6c6b38 Don't leak a file descriptor.
llvm-svn: 211699
2014-06-25 14:35:59 +00:00
Logan Chien
b6044edb18 Code cleanup.
llvm-svn: 211697
2014-06-25 13:46:17 +00:00
Chandler Carruth
4a4a94b49b Add Polly to the ignored trees.
llvm-svn: 211695
2014-06-25 13:13:36 +00:00
Chandler Carruth
2262038283 [x86] Add intrinsics for the pshufd, pshuflw, and pshufhw instructions.
llvm-svn: 211694
2014-06-25 13:12:54 +00:00
NAKAMURA Takumi
c5a2c81f7e Re-apply r211399, "Generate native unwind info on Win64" with a fix to ignore SEH pseudo ops in X86 JIT emitter.
--
This patch enables LLVM to emit Win64-native unwind info rather than
DWARF CFI.  It handles all corner cases (I hope), including stack
realignment.

Because the unwind info is not flexible enough to describe stack frames
with a gap of unknown size in the middle, such as the one caused by
stack realignment, I modified register spilling code to place all spills
into the fixed frame slots, so that they can be accessed relative to the
frame pointer.

Patch by Vadim Chugunov!

Reviewed By: rnk

Differential Revision: http://reviews.llvm.org/D4081

llvm-svn: 211691
2014-06-25 12:41:52 +00:00
NAKAMURA Takumi
35a44c8eda Reformat.
llvm-svn: 211689
2014-06-25 12:40:56 +00:00
Andrea Di Biagio
7f4e676911 [X86] Add target combine rule to select ADDSUB instructions from a build_vector
This patch teaches the backend how to combine a build_vector that implements
an 'addsub' between packed float vectors into a sequence of vector add
and vector sub followed by a VSELECT.

The new VSELECT is expected to be lowered into a BLENDI.
At ISel stage, the sequence 'vector add + vector sub + BLENDI' is
pattern-matched against ISel patterns added at r211427 to select
'addsub' instructions.
Added three more ISel patterns for ADDSUB.

Added test sse3-avx-addsub-2.ll to verify that we correctly emit 'addsub'
instructions.

llvm-svn: 211679
2014-06-25 10:02:21 +00:00