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Commit Graph

23 Commits

Author SHA1 Message Date
Benjamin Kramer
da144ed5a2 Canonicalize header guards into a common format.
Add header guards to files that were missing guards. Remove #endif comments
as they don't seem common in LLVM (we can easily add them back if we decide
they're useful)

Changes made by clang-tidy with minor tweaks.

llvm-svn: 215558
2014-08-13 16:26:38 +00:00
Eric Christopher
bbc2633ceb Make InstrInfo depend only upon the Subtarget getting passed in
rather than the TargetMachine.

llvm-svn: 213425
2014-07-18 23:25:00 +00:00
Craig Topper
adb1afb7c7 [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition
llvm-svn: 207506
2014-04-29 07:58:02 +00:00
Reed Kotler
3658d0ec5d Delete dead code.
llvm-svn: 196551
2013-12-06 00:13:50 +00:00
Reed Kotler
3d6497041f Allow the code which returns the length for inline assembler to know
specifically about the .space directive. This allows us to force large
blocks of code to appear in test cases for things like constant islands
without having to make giant test cases to force things like long 
branches to take effect.

llvm-svn: 194555
2013-11-13 04:37:52 +00:00
Reed Kotler
338c130a3e Clean up code for Mips16 large frame handling.
llvm-svn: 187701
2013-08-04 01:13:25 +00:00
Akira Hatanaka
083fece809 [mips] Rename functions. No functionality changes.
llvm-svn: 181713
2013-05-13 17:43:19 +00:00
Akira Hatanaka
fe61de70c1 [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.
No functionality changes.

llvm-svn: 178327
2013-03-29 02:14:12 +00:00
Reed Kotler
4ca11e6b77 Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.
llvm-svn: 176007
2013-02-25 02:25:47 +00:00
Reed Kotler
563b04a97f Make psuedo FEXT_T8I816_ins into a custom emitter.
llvm-svn: 176002
2013-02-24 23:17:51 +00:00
Reed Kotler
030e941124 Expand pseudos/macros:
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.

llvm-svn: 175593
2013-02-20 05:45:15 +00:00
Reed Kotler
7ddfd1de27 Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
llvm-svn: 175474
2013-02-19 00:20:58 +00:00
Reed Kotler
1ca4a75d36 Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this 
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.

llvm-svn: 175413
2013-02-18 00:59:04 +00:00
Reed Kotler
b11fbb0482 One more try to make this look nice. I have lots of pseudo lowering
as well as 16/32 bit variants to do and so I want this to look nice
when I do it. I've been experimenting with this. No new test cases
are needed.

llvm-svn: 175369
2013-02-16 19:04:29 +00:00
Reed Kotler
bb9242df63 Use a different scheme to chose 16/32 variants. This scheme is more
consistent with how BuildMI works. No new tests needed. All should work
the same as before.

llvm-svn: 175342
2013-02-16 09:47:57 +00:00
Reed Kotler
c0c9bb9263 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.

llvm-svn: 175073
2013-02-13 20:28:27 +00:00
Reed Kotler
434681ac07 When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this.
We sometimes need 2 registers for Mips16 so we must handle things
differently than how register scavenger is normally used.

llvm-svn: 174696
2013-02-08 03:57:41 +00:00
Akira Hatanaka
7477b1b91f [mips] 80 columns.
llvm-svn: 171515
2013-01-04 19:38:05 +00:00
Reed Kotler
a14be76b3b fix most of remaining issues with large frames.
these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%

llvm-svn: 170656
2012-12-20 04:07:42 +00:00
Chandler Carruth
a98c778194 Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.

Note that the script is now able to handle all of these headers without
manual edits. =]

llvm-svn: 169224
2012-12-04 07:12:27 +00:00
Reed Kotler
82a7f09a30 Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN
llvm-svn: 167107
2012-10-31 05:21:10 +00:00
Akira Hatanaka
24dddbed36 Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and
MipsSERegisterInfo.

llvm-svn: 161092
2012-07-31 23:41:32 +00:00
Akira Hatanaka
46388c74c0 Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),
and MipsSEInstrInfo (for mips32/64).

llvm-svn: 161081
2012-07-31 21:49:49 +00:00