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Commit Graph

175893 Commits

Author SHA1 Message Date
Francis Visoiu Mistrih
7f77ac0406 [OptRemarks] Make OptRemarks more generic: rename OptRemarks to Remarks
Getting rid of the name "optimization remarks" for anything that
involves handling remarks on the client side.

It's safer to do this now, before we get stuck with that name in all the
APIs and public interfaces we decide to export to users in the future.

This renames llvm/tools/opt-remarks to llvm/tools/remarks-shlib, and now
generates `libRemarks.dylib` instead of `libOptRemarks.dylib`.

Differential Revision: https://reviews.llvm.org/D58535

llvm-svn: 355439
2019-03-05 20:45:17 +00:00
Heejin Ahn
b49f808db4 [WebAssembly] Disable MachineBlockPlacement pass
Summary:
This pass hurts code size for wasm and sometimes generates irreducible
control flow.
Context: https://github.com/emscripten-core/emscripten/pull/8233

Reviewers: kripken, dschuff

Subscribers: sunfish, sbc100, jgravelle-google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58953

llvm-svn: 355437
2019-03-05 20:35:34 +00:00
Roman Lebedev
5945ae1c07 [NFC][CodeGen][X86][AArch64] Add tests for C++ std::midpoint() pattern (PR40965)
Tests only for integers, not floating point or pointers.

The scalar 8-bit case uses branch instead of CMOV,
because there is no no 8-bit CMOV.

Vector tests are for consistency, since it can be vectorized.

https://bugs.llvm.org/show_bug.cgi?id=40965

llvm-svn: 355436
2019-03-05 20:18:47 +00:00
Craig Topper
dde774575a Revert r355224 "[TableGen][SelectionDAG][X86] Add specific isel matchers for immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary."
This caused the first matcher in the isel table for many targets to Opc_Scope instead of Opc_SwitchOpcode. This leads to a significant increase in isel match failures.

llvm-svn: 355433
2019-03-05 19:18:16 +00:00
Craig Topper
69c69a340b [Subtarget] Merge ProcSched and ProcDesc arrays in MCSubtargetInfo into a single array.
These arrays are both keyed by CPU name and go into the same tablegenerated file. Merge them so we only need to store keys once.

This also removes a weird space saving quirk where we used the ProcDesc.size() to create to build an ArrayRef for ProcSched.

Differential Revision: https://reviews.llvm.org/D58939

llvm-svn: 355431
2019-03-05 18:54:38 +00:00
Guozhi Wei
8e8635f46f [X86] In X86DomainReassignment.cpp add enclosed registers to EnclosedEdges
The variable X86DomainReassignment::EnclosedEdges is used to store registers that have been enclosed in some closure, so those registers will be ignored when create new closures. But there is no registers has ever been put into this set, so a single register can be enclosed in multiple closures, it significantly increase compile time.

This patch adds a register into EnclosedEdges when it is enclosed into a closure.

Differential Revision: https://reviews.llvm.org/D58646

llvm-svn: 355430
2019-03-05 18:54:34 +00:00
Craig Topper
9cde3703c2 [Subtarget] Create a separate SubtargetSubtargetKV struct for ProcDesc to remove fields from the stack tables that aren't needed for CPUs
The description for CPUs was just the CPU name wrapped with "Select the " and " processor". We can just do that directly in the help printer instead of making a separate version in the binary for each CPU.

Also remove the Value field that isn't needed and was always 0.

Differential Revision: https://reviews.llvm.org/D58938

llvm-svn: 355429
2019-03-05 18:54:34 +00:00
Craig Topper
14fa6aa690 [Subtarget] Move SubtargetFeatureKV/SubtargetInfoKV from SubtargetFeature.h to MCSubtargetInfo.h. Move all code that operates on ProcFeatures and ProcDesc arrays to MCSubtargetInfo.
The SubtargetFeature class managed a list of features as strings. And it also had functions for setting bits in a FeatureBitset.

The methods that operated on the Feature list as strings are used in other parts of the backend. But the parts that operate on FeatureBitset are very tightly coupled to MCSubtargetInfo and requires passing in the arrays that MCSubtargetInfo owns. And the same struct type is used for ProcFeatures and ProcDesc.

This has led to MCSubtargetInfo having 2 arrays keyed by CPU name. One containing a mapping from a CPU name to its features. And one containing a mapping from CPU name to its scheduler model.

I would like to make a single CPU array containing all CPU information and remove some unneeded fields the ProcDesc array currently has. But I don't want to make SubtargetFeatures.h have to know about the scheduler model type and have to forward declare or pull in the header file.

Differential Revision: https://reviews.llvm.org/D58937

llvm-svn: 355428
2019-03-05 18:54:30 +00:00
Matt Arsenault
efd2ba88fc AMDGPU: Preserve undef flag when expanding SI_IF
Fixes undefined value verifier error.

llvm-svn: 355426
2019-03-05 18:38:00 +00:00
Craig Topper
13f2de03d3 [X86] Enable 8-bit SHL to convert to LEA
Differential Revision: https://reviews.llvm.org/D58870

llvm-svn: 355425
2019-03-05 18:37:41 +00:00
Craig Topper
29ce866ad1 [X86] Allow 8-bit INC/DEC to be converted to LEA.
We already do this for 16/32/64 as well as 8-bit add with register/immediate. Might as well do it for 8-bit INC/DEC too.

Differential Revision: https://reviews.llvm.org/D58869

llvm-svn: 355424
2019-03-05 18:37:37 +00:00
Craig Topper
2bcecae492 [X86] Enable 8-bit OR with disjoint bits to convert to LEA
We already support 8-bits adds in convertToThreeAddress. But we can also support 8-bit OR if the bits are disjoint. We already do this for 16/32/64.

Differential Revision: https://reviews.llvm.org/D58863

llvm-svn: 355423
2019-03-05 18:37:33 +00:00
Florian Hahn
b06b894c1f [SLP] Fix invalid triple in X86 tests
x86-64 is an invalid architecture in triples. Changing it to the correct
triple (x86_64) changes some tests, because SLP is not deemed profitable
any more.

Reviewers: ABataev, RKSimon, spatel

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D58931

llvm-svn: 355420
2019-03-05 17:56:35 +00:00
Javed Absar
d19970f650 TableGen: Allow lists to be concatenated through '#'
Currently one can concatenate strings using hash(#),
but not lists, although that would be a natural thing to do. 

This patch allows one to write something like:
def : A<!listconcat([1,2], [3,4])>;
simply as :
def : A<[1,2] # [3,4]>;

This was missing feature was highlighted by Nicolai
at FOSDEM talk.

Reviewed by: nhaehnle, hfinkel

Differential Revision: https://reviews.llvm.org/D58895

llvm-svn: 355414
2019-03-05 17:16:07 +00:00
Simon Pilgrim
dcde6a778e [X86][SSE] Regenerate vector zero tests
llvm-svn: 355412
2019-03-05 16:52:14 +00:00
Sanjay Patel
afd4ff2eee [SDAG] move FP constant folding to helper function; NFC
llvm-svn: 355411
2019-03-05 16:42:33 +00:00
Jessica Paquette
1b3a1b13fd Revert "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT"
This broke test-suite::aarch64_neon_intrinsics.test

Reverting while I look into it.

Example failure:
http://lab.llvm.org:8011/builders/clang-cmake-aarch64-quick/builds/17740

llvm-svn: 355408
2019-03-05 15:47:00 +00:00
Simon Pilgrim
c09a0f009a [X86] Add SMULO/UMULO combine tests
Include scalar and vector test variants covering the folds in DAGCombiner (vector isn't currently supported - PR40442)

llvm-svn: 355407
2019-03-05 15:36:45 +00:00
Simon Pilgrim
c38f14aa87 Fix typo in constant vector
llvm-svn: 355405
2019-03-05 15:06:01 +00:00
Simon Pilgrim
6e9b6a15d2 [X86] Add SADDO/UADDO and SSUBO/USUBO combine tests
Include scalar and vector test variants covering the folds in DAGCombiner (vector isn't currently supported - PR40442)

llvm-svn: 355404
2019-03-05 14:52:42 +00:00
Simon Pilgrim
2542538e6e [X86] Add test cases for D58874
Add scalar and vector test cases for missing (add (add (xor a, -1), b), 1) -> (sub b, a) fold

llvm-svn: 355400
2019-03-05 13:52:09 +00:00
George Rimar
e24ba5947b [llvm-objcopy] - Simplify isCompressable and fix the issue relative.
When --compress-debug-sections is given, llvm-objcopy do not compress
sections that have "ZLIB" header in data. Normally this signature is used
in zlib-gnu compression format. But if zlib-gnu used then the name of the compressed
section should start from .z* (e.g .zdebug_info). If it does not, then it is not
a zlib-gnu format and section should be treated as a normal uncompressed section.

Differential revision: https://reviews.llvm.org/D58908

llvm-svn: 355399
2019-03-05 13:07:43 +00:00
Carl Ritson
c6a3af137e [AMDGPU] Fix DPP operand order in atomic optimizer
Summary:
Ensure order of operands in DPP atomic optimizer final WWM step is appropriate for sub instructions.

Change-Id: I631d050e1c00a3b4bc7c11a90437064403c4cf30

Reviewers: sheredom, tpr

Reviewed By: sheredom

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58900

llvm-svn: 355394
2019-03-05 12:21:44 +00:00
David Green
56efa959c1 [SCEV] Ensure that isHighCostExpansion takes into account what is being divided
A SCEV is not low-cost just because you can divide it by a power of 2. We need to also
check what we are dividing to make sure it too is not a high-code expansion. This helps
to not expand the exit value of certain loops, helping not to bloat the code.

The change in no-iv-rewrite.ll is reverting back to what it was testing before rL194116,
and looks a lot like the other tests in replace-loop-exit-folds.ll.

Differential Revision: https://reviews.llvm.org/D58435

llvm-svn: 355393
2019-03-05 12:12:18 +00:00
George Rimar
d6ec2efde8 [llvm-objcopy] - Report "no zlib available" error properly when --compress-debug-sections is used.
If zlib is not available, and --compress-debug-sections is passed, 
we want to report an error. Currently, it is only reported for
--compress_debug_sections= form of the option.

Fixes the https://bugs.llvm.org/show_bug.cgi?id=40886.

I do not think there is a way to write a test for this.

Differential revision: https://reviews.llvm.org/D58909

llvm-svn: 355391
2019-03-05 11:32:14 +00:00
David Green
fe77953df8 [SCEV] Add some extra tests for IndVarSimplifys loop exit values. NFC.
Add some tests for various loops of the form:
  while(S >= 32) {
    S -= 32;
    something();
  };
  return S;

llvm-svn: 355389
2019-03-05 11:18:55 +00:00
Heejin Ahn
e7448c19c9 [WebAssembly] Rename a variable in LateEHPrepare (NFC)
llvm-svn: 355387
2019-03-05 11:11:34 +00:00
Simon Pilgrim
837d55ff6d Add wildcard support to all update_*_test_checks.py scripts (PR37500)
We can already update multiple files in each update call, this extends it to work with wildcards as well in the same way as update_mca_test_checks.py (to support shells that won't do this for us - windows command prompt etc.)

Differential Revision: https://reviews.llvm.org/D58817

llvm-svn: 355386
2019-03-05 10:44:37 +00:00
Oliver Stannard
3d36623349 [ARM] Fix select_cc lowering for fp16
When lowering a select_cc node where the true and false values are of type f16,
we can't use a general conditional move because the FP16 instructions do not
support conditional execution. Instead, we must ensure that the condition code
is one of the four supported by the VSEL instruction.

Differential revision: https://reviews.llvm.org/D58813

llvm-svn: 355385
2019-03-05 10:42:34 +00:00
David Stuttard
bb37713abf [AMDGPU] Omit KILL instructions from hazard recognizer
Summary:
In some cases the KILL was causing a hazard to be introduced as these were
scheduled into hazard slots, but don't result in an instruction.

KILL shouldn't be considered for hazard recognition.

Change-Id: Ib6d2a2160f8c94cd0ce611ab198c7e4f46aeffcf

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58898

llvm-svn: 355384
2019-03-05 10:25:16 +00:00
Craig Topper
410a517f82 [LangRef] Add 'callbr' instruction to the 'blockaddress' section.
llvm-svn: 355379
2019-03-05 05:23:37 +00:00
Chen Zheng
7f925b398f [PowerPC] fix killed/dead flag after convert x-form to d-form tranformation.
Differential Revision: https://reviews.llvm.org/D58428

llvm-svn: 355378
2019-03-05 04:56:54 +00:00
Xing GUO
22917f076e [ARM][MC] Update one test case in 'test/MC/Disassembler/ARM/invalid-armv7.txt'
Summary:
Instruction `[0xfe 0xf0 0x20 0xe3]` is a valid instruction on ARM-v7, which is `dbg #14`. See: 
https://www.cl.cam.ac.uk/research/srg/han/ACS-P35/zynq/ARMv7-A-R-manual.pdf 
(Page: 377)

```
Encoding A1:
DBG<c> #<option>

|31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16|15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00|
|      cond | 0  0  1  1  0| 0| 1  0| 0  0  0  0| 1  1  1  1| 0  0  0  0| 1  1  1  1|    option |
```

Reviewers: fhahn, efriedma

Reviewed By: efriedma

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58873

llvm-svn: 355374
2019-03-05 03:07:56 +00:00
Scott Linder
7f3e1f67de [AMDGPU] Implement AMDGPUMCInstrAnalysis
Implement MCInstrAnalysis for AMDGPU, with default implementations save
for `evaluateBranch`.

Differential Revision: https://reviews.llvm.org/D58400

llvm-svn: 355373
2019-03-05 03:02:00 +00:00
Sanjoy Das
5012dbbadd PHI nodes are not FPMathOperator s
Reviewers: chandlerc, arsenm

Reviewed By: arsenm

Subscribers: wdng, arsenm, mcrosier, jlebar, bixia, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58887

llvm-svn: 355362
2019-03-05 01:15:08 +00:00
Craig Topper
a47507ca88 [X86] Reduce some patterns by using FP instructions for integer types even when AVX2 is available and execution domain fixing will do the right thing
We have quite a few cases of using FP instructions for integer operations when only AVX1 is available. Then we switch to integer instructions with AVX2. In a lot of these cases execution domain fixing will take care of turning FP instructions into integer if its profitable.

With this patch we just keep on using the FP instructions even with AVX2. I've only handled some cases that don't require messing with patterns that are defined in the instruction definition. Those will require more subtle multiclass work possibly involving null_frag, hasSideEffects = 0, etc.

Differential Revision: https://reviews.llvm.org/D58470

llvm-svn: 355361
2019-03-05 01:14:25 +00:00
Yonghong Song
4e71c14bf1 [BPF] Do not generate BTF sections unnecessarily
If There is no types/non-empty strings, do not generate
.BTF section. If there is no func_info/line_info, do
not generate .BTF.ext section.

Signed-off-by: Yonghong Song <yhs@fb.com>

Differential Revision: https://reviews.llvm.org/D58936

llvm-svn: 355360
2019-03-05 01:01:21 +00:00
Shoaib Meenai
25c7018595 [cmake] Create exports for umbrella library targets
When using the umbrella llvm-libraries and clang-libraries targets, we
should export all library targets, otherwise they'll be part of our
distribution but not usable from the CMake package.

Differential Revision: https://reviews.llvm.org/D58862

llvm-svn: 355354
2019-03-05 00:38:32 +00:00
Florian Hahn
70c79335f4 Fix invalid target triples in tests. (NFC)
llvm-svn: 355349
2019-03-04 23:37:41 +00:00
Evgeniy Stepanov
973bc4b579 [msan] Instrument x86 BMI intrinsics.
Summary:
They simply shuffle bits. MSan needs to do the same with shadow bits,
after making sure that the shuffle mask is fully initialized.

Reviewers: pcc, vitalybuka

Subscribers: hiraditya, #sanitizers, llvm-commits

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D58858

llvm-svn: 355348
2019-03-04 22:58:20 +00:00
Jordan Rupprecht
6daafbf4be [NFC] Fix PGO link error in shared libs build
llvm-svn: 355346
2019-03-04 22:54:44 +00:00
Sanjay Patel
8f1017e9ee [CodeGenPrepare] avoid crashing on non-canonical/degenerate code
The test is reduced from an example in the post-commit thread for:
rL354746
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20190304/632396.html

While we must avoid dying here, the real question should be:
Why is non-canonical and/or degenerate code making it to CGP when
using the new pass manager?

llvm-svn: 355345
2019-03-04 22:47:13 +00:00
Jessica Paquette
dd5c010238 [GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT
This adds instruction selection support for G_EXTRACT_VECTOR_ELT for cases
where the index is defined by a G_CONSTANT.

It also factos out the lane copy opcode selection part into its own function,
`getLaneCopyOpcode`. This is used by both `selectUnmergeValues` and
`selectExtractElt`.

Differential Revision: https://reviews.llvm.org/D58469

llvm-svn: 355344
2019-03-04 22:35:32 +00:00
Shoaib Meenai
f5bbfca8c1 [build] Rename clang-headers to clang-resource-headers
Summary:
The current install-clang-headers target installs clang's resource
directory headers. This is different from the install-llvm-headers
target, which installs LLVM's API headers. We want to introduce the
corresponding target to clang, and the natural name for that new target
would be install-clang-headers. Rename the existing target to
install-clang-resource-headers to free up the install-clang-headers name
for the new target, following the discussion on cfe-dev [1].

I didn't find any bots on zorg referencing install-clang-headers. I'll
send out another PSA to cfe-dev to accompany this rename.

[1] http://lists.llvm.org/pipermail/cfe-dev/2019-February/061365.html

Reviewers: beanz, phosek, tstellar, rnk, dim, serge-sans-paille

Subscribers: mgorny, javed.absar, jdoerfert, #sanitizers, openmp-commits, lldb-commits, cfe-commits, llvm-commits

Tags: #clang, #sanitizers, #lldb, #openmp, #llvm

Differential Revision: https://reviews.llvm.org/D58791

llvm-svn: 355340
2019-03-04 21:19:53 +00:00
Jessica Paquette
aff4683104 [GlobalISel][AArch64] Legalize vector G_SELECT
Just scalarize it, and add a test showing it works.

Differential Revision: https://reviews.llvm.org/D58747

llvm-svn: 355339
2019-03-04 21:12:46 +00:00
Evgeniy Stepanov
135b61b60c Fix wrong enum value in switch.
llvm-svn: 355338
2019-03-04 21:00:28 +00:00
Sanjay Patel
14a0e6ae7d [ConstantHoisting] avoid hang/crash from unreachable blocks (PR40930)
I'm not too familiar with this pass, so there might be a better
solution, but this appears to fix the degenerate:
PR40930
PR40931
PR40932
PR40934
...without affecting any real-world code.

As we've seen in several other passes, when we have unreachable blocks,
they can contain semi-bogus IR and/or cause unexpected conditions. We
would not typically expect these patterns to make it this far, but we
have to guard against them anyway.

llvm-svn: 355337
2019-03-04 20:57:14 +00:00
Rong Xu
888aa59db9 [PGO] Context sensitive PGO (part 3)
Part 3 of CSPGO changes (mostly related to PassMananger).

Differential Revision: https://reviews.llvm.org/D54175

llvm-svn: 355330
2019-03-04 20:21:27 +00:00
Nikita Popov
49583d4c43 [InstCombine] Add tests for add nsw + sadd.with.overflow; NFC
Baseline tests for D58881, which fixes part of PR38146.

Patch by Dan Robertson.

llvm-svn: 355328
2019-03-04 19:35:46 +00:00
Craig Topper
de4af9e7d5 [Subtarget] Follow up to r355167, add another set of curly braces to FeatureBitArray initialization to satisfy older versions of clang.
Apparently older versions of clang like 3.6 require an extra set of curly braces around std::array initializations. I'm told the C++ language was changed regarding this by CWG 1270.

llvm-svn: 355327
2019-03-04 19:23:37 +00:00