Evan Cheng
f583b3feb6
64-bit atomic operations.
...
llvm-svn: 49949
2008-04-19 02:30:38 +00:00
Evan Cheng
09e77f6b83
PPC32 atomic operations.
...
llvm-svn: 49947
2008-04-19 01:30:48 +00:00
Dan Gohman
c9dec33f3f
Add support for multiple return values for the PPC target by
...
converting call result lowering to use the CallingConvLowering
infastructure.
llvm-svn: 48552
2008-03-19 21:39:28 +00:00
Scott Michel
bb8e8fca47
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
...
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
Dale Johannesen
86867d323e
Move PPC lowering functions into PPCTargetLowering
...
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
llvm-svn: 47917
2008-03-04 23:17:14 +00:00
Dale Johannesen
310201ba32
Interface of getByValTypeAlignment differed between
...
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
llvm-svn: 47734
2008-02-28 22:31:51 +00:00
Dan Gohman
99b38405e3
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
...
to pass the mask APInt by value, not by reference.
llvm-svn: 47096
2008-02-13 22:28:48 +00:00
Dan Gohman
09023887f8
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
...
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
llvm-svn: 47039
2008-02-13 00:35:47 +00:00
Evan Cheng
918b9c9335
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
...
instruction at the end.
llvm-svn: 46562
2008-01-30 18:18:23 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
...
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Chris Lattner
e16166b78d
implement __builtin_return_addr(0) on ppc.
...
llvm-svn: 44700
2007-12-08 06:59:59 +00:00
Chris Lattner
e59a7ee26a
Implement ExpandOperationResult for ppc i64 fp->int, which fixes
...
CodeGen/Generic/fp_to_int.ll among others. Its unclear why this
just started failing...
llvm-svn: 44407
2007-11-28 18:44:47 +00:00
Dale Johannesen
76458ddf1e
Next PPC long double bits: ppcf128->i32 conversion.
...
Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).
llvm-svn: 42822
2007-10-10 01:01:31 +00:00
Chris Lattner
1e089aac3a
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
...
changing the interface to allow for future changes.
llvm-svn: 41384
2007-08-25 00:47:38 +00:00
Dan Gohman
352de5aeb9
More explicit keywords.
...
llvm-svn: 40757
2007-08-02 21:21:54 +00:00
Evan Cheng
ff50061170
Vector fneg must be expanded into fsub -0.0, X.
...
llvm-svn: 40586
2007-07-30 07:51:22 +00:00
Dan Gohman
a62327ea40
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
Nicolas Geoffray
681a87d9e8
Starting implementation of the ELF32 ABI specification of varargs handling.
...
LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.
llvm-svn: 35625
2007-04-03 13:59:52 +00:00
Chris Lattner
c0405a348d
implement the new addressing mode description hook.
...
llvm-svn: 35521
2007-03-30 23:15:24 +00:00
Chris Lattner
b19069959d
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
Evan Cheng
06d83c8fce
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
...
llvm-svn: 35074
2007-03-12 23:29:01 +00:00
Nicolas Geoffray
4b5b81198a
Implemented the frameaddress intrinsic for PPC.
...
llvm-svn: 34787
2007-03-01 13:11:38 +00:00
Nicolas Geoffray
a562e5c1c5
Differentiate between the MachO and the ELF ABI the CALL instruction.
...
llvm-svn: 34667
2007-02-27 13:01:19 +00:00
Chris Lattner
041fb5bc67
implement support for the linux/ppc function call ABI. Patch by
...
Nicolas Geoffray!
llvm-svn: 34574
2007-02-25 05:34:32 +00:00
Nate Begeman
80d913651d
Fix a spelling error
...
llvm-svn: 33556
2007-01-26 22:40:50 +00:00
Jim Laskey
8aac7dc0ee
This is a general clean up of the PowerPC ABI. Address several problems and
...
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.
llvm-svn: 31792
2006-11-16 22:43:37 +00:00
Evan Cheng
89ee587963
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
Chris Lattner
bd39c99fd1
Refactor all the addressing mode selection stuff into the isel lowering
...
class, where it can be used for preinc formation.
llvm-svn: 31536
2006-11-08 02:15:41 +00:00
Chris Lattner
38c04a6bd6
Implement the getRegForInlineAsmConstraint method for PPC. With recent
...
sdisel changes, this eliminates a ton of copies around common inline asms.
For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
llvm-svn: 31367
2006-11-02 01:44:04 +00:00
Chris Lattner
d9afd310a6
Change the prototype for TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31318
2006-10-31 19:40:43 +00:00
Reid Spencer
2567610703
For PR387:
...
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.
llvm-svn: 29934
2006-08-28 01:02:49 +00:00
Chris Lattner
abaaddc214
Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
...
into i16/i32 load/stores.
llvm-svn: 29089
2006-07-10 20:56:58 +00:00
Chris Lattner
2208c3214c
Make PPC call lowering more aggressive, making the isel matching code simple
...
enough to be autogenerated.
llvm-svn: 28354
2006-05-17 19:00:46 +00:00
Chris Lattner
b5271a0f4c
Instead of implementing LowerCallTo directly, let the default impl produce an
...
ISD::CALL node, then custom lower that. This means that we only have to handle
LEGAL call operands/results, not every possible type. This allows us to
simplify the call code, shrinking it by about 1/3.
llvm-svn: 28339
2006-05-16 22:56:08 +00:00
Chris Lattner
0a12e343e2
Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument
...
handling. This makes the lower argument code significantly simpler (we
only need to handle legal argument types).
Incidentally, this also implements support for vector argument registers,
so long as they are not on the stack.
llvm-svn: 28331
2006-05-16 18:18:50 +00:00
Chris Lattner
44ea12c5f8
Implement an important entry from README_ALTIVEC:
...
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
llvm-svn: 27804
2006-04-18 17:59:36 +00:00
Chris Lattner
ce6e988fa6
Rename get_VSPLI_elt -> get_VSPLTI_elt
...
Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively. This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI
llvm-svn: 27614
2006-04-12 17:37:20 +00:00
Chris Lattner
e8defcff7d
Change the interface to the predicate that determines if vsplti* can be used.
...
No functionality changes.
llvm-svn: 27536
2006-04-08 06:46:53 +00:00
Chris Lattner
c0680ae07e
Match vpku[hw]um(x,x).
...
Convert vsldoi(x,x) to work the same way other (x,x) cases work.
llvm-svn: 27467
2006-04-06 22:28:36 +00:00
Chris Lattner
a52d88ee89
Add support for matching vmrg(x,x) patterns
...
llvm-svn: 27463
2006-04-06 22:02:42 +00:00
Chris Lattner
300076cbd8
Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles.
...
llvm-svn: 27457
2006-04-06 21:11:54 +00:00
Chris Lattner
2875bb116e
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to
...
lower it and LLVM to have one fewer intrinsic. This implements
CodeGen/PowerPC/vec_shuffle.ll
llvm-svn: 27450
2006-04-06 18:26:28 +00:00
Chris Lattner
10fa7be550
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
...
vperm with a perm mask lvx'd from the constant pool.
llvm-svn: 27448
2006-04-06 17:23:16 +00:00
Chris Lattner
4e99e6dfdd
Ask legalize to promote all vector shuffles to be v16i8 instead of having to
...
handle all 4 PPC vector types. This simplifies the matching code and allows
us to eliminate a bunch of patterns. This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.
llvm-svn: 27400
2006-04-04 17:25:31 +00:00
Chris Lattner
8ba4723c74
Inform the dag combiner that the predicate compares only return a low bit.
...
llvm-svn: 27359
2006-04-02 06:26:07 +00:00
Chris Lattner
e330741a6c
Lower vector compares to VCMP nodes, just like we lower vector comparison
...
predicates to VCMPo nodes.
llvm-svn: 27285
2006-03-31 05:13:27 +00:00
Chris Lattner
ac98e20cc9
Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
...
same thing and we have a dag node for the former.
llvm-svn: 27205
2006-03-28 01:43:22 +00:00
Chris Lattner
65a455b060
Codegen vector predicate compares.
...
llvm-svn: 27151
2006-03-26 10:06:40 +00:00
Evan Cheng
b17bbf8ccb
Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead
...
llvm-svn: 27149
2006-03-26 09:52:32 +00:00
Chris Lattner
0899b16b2d
Codegen things like:
...
<int -1, int -1, int -1, int -1>
and
<int 65537, int 65537, int 65537, int 65537>
Using things like:
vspltisb v0, -1
and:
vspltish v0, 1
instead of using constant pool loads.
This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.
llvm-svn: 27106
2006-03-25 06:12:06 +00:00