Eric Christopher
91d4c0078f
Typo.
...
llvm-svn: 160981
2012-07-30 20:09:37 +00:00
Kevin Enderby
cde92a2741
Fix a bug in ARMMachObjectWriter::RecordRelocation() in ARMMachObjectWriter.cpp
...
where the other_half of the movt and movw relocation entries needs to get set
and only with the 16 bits of the other half.
rdar://10038370
llvm-svn: 160978
2012-07-30 18:46:15 +00:00
Jakob Stoklund Olesen
7bbe0b0328
Add MachineInstr::isTransient().
...
This is a cleaned up version of the isFree() function in
MachineTraceMetrics.cpp.
Transient instructions are very unlikely to produce any code in the
final output. Either because they get eliminated by RegisterCoalescing,
or because they are pseudo-instructions like labels and debug values.
llvm-svn: 160977
2012-07-30 18:34:14 +00:00
Jakob Stoklund Olesen
c3b8765d57
Add MachineTraceMetrics::verify().
...
This function verifies the consistency of cached data in the
MachineTraceMetrics analysis.
llvm-svn: 160976
2012-07-30 18:34:11 +00:00
Jakob Stoklund Olesen
6653a31973
Verify that the CFG hasn't changed during invalidate().
...
The MachineTraceMetrics analysis must be invalidated before modifying
the CFG. This will catch some of the violations of that rule.
llvm-svn: 160969
2012-07-30 17:36:49 +00:00
Jakob Stoklund Olesen
4f3254f73c
Add MachineBasicBlock::isPredecessor().
...
A->isPredecessor(B) is the same as B->isSuccessor(A), but it can
tolerate a B that is null or dangling. This shouldn't happen normally,
but it it useful for verification code.
llvm-svn: 160968
2012-07-30 17:36:47 +00:00
Nadav Rotem
1fbb339620
When constant folding GEP expressions, keep the address space information of pointers.
...
Together with Ran Chachick <ran.chachick@intel.com>
llvm-svn: 160954
2012-07-30 07:25:20 +00:00
Craig Topper
f374fd0e17
Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoad
...
llvm-svn: 160953
2012-07-30 07:14:07 +00:00
Craig Topper
19fc5055ea
Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.
...
llvm-svn: 160951
2012-07-30 06:48:11 +00:00
Craig Topper
63cf938ced
Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly
...
llvm-svn: 160950
2012-07-30 06:27:19 +00:00
Craig Topper
f02d9cd605
Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already.
...
llvm-svn: 160949
2012-07-30 05:39:34 +00:00
Craig Topper
a78fdabf13
Simplify code that filtered certain instructions in two different ways. No functional change.
...
llvm-svn: 160948
2012-07-30 05:10:05 +00:00
Craig Topper
5e5b8cbcd3
Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway.
...
llvm-svn: 160946
2012-07-30 04:53:00 +00:00
Craig Topper
8afab784a4
Remove trailing whitespace.
...
llvm-svn: 160945
2012-07-30 04:48:12 +00:00
Craig Topper
80fdfb7f56
Give VCVTTPD2DQ priority over CVTTPD2DQ.
...
llvm-svn: 160942
2012-07-30 02:20:32 +00:00
Craig Topper
492a7af190
Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.
...
llvm-svn: 160941
2012-07-30 02:14:02 +00:00
Craig Topper
9050c15c71
Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern.
...
llvm-svn: 160939
2012-07-30 01:38:57 +00:00
Craig Topper
147248a6a0
Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert instruction patterns.
...
llvm-svn: 160938
2012-07-29 23:26:34 +00:00
Craig Topper
293e781ba6
Move more SSE/AVX convert instruction patterns into their definitions.
...
llvm-svn: 160937
2012-07-29 22:30:06 +00:00
Benjamin Kramer
42c85ae9d5
APInt: Simplify code.
...
No functionality change.
llvm-svn: 160929
2012-07-29 12:33:29 +00:00
Manman Ren
ceef7c4d9b
Revert r160920 and r160919 due to dragonegg and clang selfhost failure
...
llvm-svn: 160927
2012-07-29 02:44:09 +00:00
Nick Lewycky
a1eb0b5f2e
Add testcases for GlobalOpt changes in r160693 and r160757.
...
llvm-svn: 160925
2012-07-29 01:15:37 +00:00
Craig Topper
e75418242a
Fold patterns for some of the SSE/AVX convert instructions into their instruction definitions.
...
llvm-svn: 160922
2012-07-28 18:59:19 +00:00
Craig Topper
189349dab2
Mark some of the SSE/AVX convert instructions as mayLoad/neverHasSideEffects.
...
llvm-svn: 160921
2012-07-28 18:36:39 +00:00
Manman Ren
9494d0a2c2
X86 Peephole: fold loads to the source register operand if possible.
...
Trying to fix the bot by specifying a triple in the failing testing cases.
llvm-svn: 160920
2012-07-28 17:51:24 +00:00
Manman Ren
ea77f9076b
X86 Peephole: fold loads to the source register operand if possible.
...
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.
rdar://10554090 and rdar://11873276
llvm-svn: 160919
2012-07-28 16:48:01 +00:00
Craig Topper
3c15b4afd4
Make CVTSS2SI instruction definition consistent with CVTSD2SI.
...
llvm-svn: 160914
2012-07-28 08:28:23 +00:00
Craig Topper
8121932592
Fix up memory load types for SSE scalar convert intrinsic patterns.
...
llvm-svn: 160913
2012-07-28 07:59:59 +00:00
Manman Ren
fbc9fcdbf2
X86 Peephole: fix PR13475 in optimizeCompare.
...
It is possible that an instruction can use and update EFLAGS.
When checking the safety, we should check the usage of EFLAGS first before
declaring it is safe to optimize due to the update.
llvm-svn: 160912
2012-07-28 03:15:46 +00:00
Andrew Trick
0320969afa
Reenable a basic SSA DAG builder optimization.
...
Jakob fixed ProcessImplicifDefs in r159149.
llvm-svn: 160910
2012-07-28 01:48:15 +00:00
Jakob Stoklund Olesen
0eacb18967
Add more debug output to MachineTraceMetrics.
...
llvm-svn: 160905
2012-07-27 23:58:38 +00:00
Jakob Stoklund Olesen
fefd43f7a9
Keep track of the head and tail of the trace through each block.
...
This makes it possible to quickly detect blocks that are outside the
trace.
llvm-svn: 160904
2012-07-27 23:58:36 +00:00
Eric Christopher
acd91c534d
Add a DW_AT_high_pc for CUs that are a single address range. Update
...
all tests accordingly.
Fixes PR13351.
Patch by shinichiro hamaji!
llvm-svn: 160899
2012-07-27 22:00:05 +00:00
Jakob Stoklund Olesen
88319a3e66
Also compute register mask lists under -new-live-intervals.
...
llvm-svn: 160898
2012-07-27 21:56:39 +00:00
Chad Rosier
6584b9fc2d
Typos.
...
llvm-svn: 160897
2012-07-27 21:41:59 +00:00
Evan Cheng
f318924b28
Teach CodeGenPrep to look past bitcast when it's duplicating return instruction
...
into predecessor blocks to enable tail call optimization.
rdar://11958338
llvm-svn: 160894
2012-07-27 21:21:26 +00:00
Jakob Stoklund Olesen
8e957f3c0b
Eliminate the IS_PHI_DEF flag and VNInfo::setIsPHIDef().
...
A value number is a PHI def if and only if it begins at a block
boundary. This can be derived from the def slot, a separate flag is not
necessary.
llvm-svn: 160893
2012-07-27 21:11:14 +00:00
Jakob Stoklund Olesen
d60f4942e6
Add a -new-live-intervals experimental option.
...
This option replaces the existing live interval computation with one
based on LiveRangeCalc.cpp. The new algorithm does not depend on
LiveVariables, and it can be run at any time, before or after leaving
SSA form.
llvm-svn: 160892
2012-07-27 20:58:46 +00:00
Andrew Kaylor
06f27a2297
Fixing problems with X86_64_32 relocations and making the assertions more readable.
...
llvm-svn: 160889
2012-07-27 20:30:12 +00:00
Jakob Stoklund Olesen
03a59af504
Add <imp-def> of super-register when lowering SUBREG_TO_REG.
...
Patch by Tyler Nowicki!
llvm-svn: 160888
2012-07-27 20:19:49 +00:00
Benjamin Kramer
ccda787c4d
SmallVector: Crank up verbosity of asserts per Chandler's request.
...
Also add assertions to validate the iterator in the insert method overloads.
llvm-svn: 160882
2012-07-27 19:05:58 +00:00
Chad Rosier
e8c032f7f0
The TimePassesIsEnabled has since moved to PassManager.cpp.
...
llvm-svn: 160881
2012-07-27 19:03:02 +00:00
Andrew Kaylor
b417406b7b
Test commit, clean up comment
...
llvm-svn: 160880
2012-07-27 18:39:47 +00:00
Nuno Lopes
a4d7ce1441
fix PR13390: do not loop forever with self-referencing self instructions
...
llvm-svn: 160876
2012-07-27 18:21:15 +00:00
Nuno Lopes
7ec9936cb2
fix infinite loop in instcombine in the presence of a (malformed) self-referencing select inst.
...
This can happen as long as the instruction is not reachable. Instcombine does generate these unreachable malformed selects when doing RAUW
llvm-svn: 160874
2012-07-27 18:03:57 +00:00
Andrew Kaylor
4ef7c7305d
Test commit, clean up comment
...
llvm-svn: 160873
2012-07-27 17:52:42 +00:00
Jakob Stoklund Olesen
234fac2188
Give MCRegisterInfo an implementation file.
...
Move some functions from MCRegisterInfo.h that don't need to be inline.
This shrinks llc by 8K.
llvm-svn: 160865
2012-07-27 16:25:20 +00:00
Benjamin Kramer
29c0b4a9f7
SmallVector::erase: Assert that iterators are actually inside the vector.
...
The rationale here is that it's hard to write loops containing vector erases and
it only shows up if the vector contains non-trivial objects leading to crashes
when forming them out of garbage memory.
llvm-svn: 160854
2012-07-27 09:10:25 +00:00
Craig Topper
043e2ac679
Clean up includes.
...
llvm-svn: 160852
2012-07-27 06:44:02 +00:00
Jakob Stoklund Olesen
49c17daace
Eliminate the large XXXSubRegTable constant arrays.
...
These tables were indexed by [register][subreg index] which made them,
very large and sparse.
Replace them with lists of sub-register indexes that match the existing
lists of sub-registers. MCRI::getSubReg() becomes a very short linear
search, like getSubRegIndex() already was.
llvm-svn: 160843
2012-07-27 00:10:51 +00:00