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5 Commits

Author SHA1 Message Date
Eli Friedman
c60a0ad611 Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289. 
llvm-svn: 143498
 2011-11-01 21:18:39 +00:00
Benjamin Kramer
c0001c42c6 X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in. 
llvm-svn: 143315
 2011-10-30 17:31:21 +00:00
Nadav Rotem
8282fc9e3b Fix pr11266. 
On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.

llvm-svn: 143311
 2011-10-30 13:24:22 +00:00
Nadav Rotem
8ed6f090ef Enable element promotion type legalization by deafault. 
Changed tests which assumed that vectors are legalized by widening them.

llvm-svn: 142152
 2011-10-16 20:31:33 +00:00
Nadav Rotem
2a654a69ed Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector. 
llvm-svn: 131179
 2011-05-11 08:12:09 +00:00