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841a1fce67
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48086 Commits

Author SHA1 Message Date
Lang Hames
841a1fce67 Make GVN look through extractvalues for recognised intrinsics. GVN can then CSE ops that match values produced by the intrinsics. 
llvm-svn: 134677
 2011-07-08 01:50:54 +00:00
Akira Hatanaka
3249cd6612 Raise assertion when MachineOperand has unexpected target flag. 
llvm-svn: 134671
 2011-07-08 00:42:35 +00:00
Akira Hatanaka
a1dfe93665 Make sure variable Kind is assigned a value to suppress warning. 
llvm-svn: 134668
 2011-07-08 00:26:25 +00:00
Nick Lewycky
a82f7a687e Let the inline asm 'q' constraint match float, and on 64-bit double too. 
Fixes PR9602!

llvm-svn: 134665
 2011-07-08 00:19:27 +00:00
Eric Christopher
5fb023bb10 Go ahead and emit the barrier on x86-64 even without sse2. The 
processor supports it just fine.

Fixes PR9675 and rdar://9740801

llvm-svn: 134664
 2011-07-08 00:04:56 +00:00
Akira Hatanaka
90fcf55a54 Lower MachineInstr to MC Inst and print to .s files. 
llvm-svn: 134661
 2011-07-07 23:56:50 +00:00
Eric Christopher
96527f39fd Handle fpcr register. 
Part of PR10299 and rdar://9740322

llvm-svn: 134653
 2011-07-07 22:54:12 +00:00
Eric Christopher
b7597bc669 Add support for the X86 'l' constraint. 
Fixes PR10149 and rdar://9738585

llvm-svn: 134648
 2011-07-07 22:29:07 +00:00
Eric Christopher
f3059adb4b Remove a FIXME. All of the standard ones are in the list. 
llvm-svn: 134647
 2011-07-07 22:29:03 +00:00
Akira Hatanaka
e3bcd9ec0a Remove unnecessary newline. 
llvm-svn: 134645
 2011-07-07 22:06:18 +00:00
Devang Patel
f97af90b4a Add DEBUG message. 
llvm-svn: 134643
 2011-07-07 21:44:42 +00:00
Evan Cheng
bbed81df25 Add Mode64Bit feature and sink it down to MC layer. 
llvm-svn: 134641
 2011-07-07 21:06:52 +00:00
Bill Wendling
49b8e85286 Move a function out-of-line. 
llvm-svn: 134640
 2011-07-07 21:05:13 +00:00
Akira Hatanaka
ccdaa7946c Rather than having printMemOperand change the way memory operands are printed 
based on a modifier, split it into two functions.

llvm-svn: 134637
 2011-07-07 20:54:20 +00:00
Akira Hatanaka
b4c145253b This patch adds a flag in MCAsmInfo that indicates whether dwarf register 
numbers should be printed instead of symbolic register names in
MCAsmStreamer::EmitRegisterName. This is necessary because some versions of
GNU assembler won't accept code in which symbolic register names are used in
cfi directives. There is no change in behavior unless the flag is explicitly
set to true by a backend.

llvm-svn: 134635
 2011-07-07 20:30:33 +00:00
Akira Hatanaka
9cddf51671 Define class MipsMCInstLower. 
llvm-svn: 134633
 2011-07-07 20:24:54 +00:00
Akira Hatanaka
382742199f Change visibility of MipsAsmPrinter. 
llvm-svn: 134630
 2011-07-07 20:10:52 +00:00
Akira Hatanaka
b5f9a0486c Define class MipsMCSymbolRefExpr. 
llvm-svn: 134629
 2011-07-07 19:27:22 +00:00
Akira Hatanaka
0de1fce485 Simplify MipsRegisterInfo::eliminateFrameIndex. 
llvm-svn: 134628
 2011-07-07 19:13:09 +00:00
Evan Cheng
dbc4dc612a Rewrite comment in English. 
llvm-svn: 134627
 2011-07-07 19:09:06 +00:00
Evan Cheng
faa59a86f1 Rename attribute 'thumb' to a more descriptive 'thumb-mode'. 
llvm-svn: 134626
 2011-07-07 19:05:12 +00:00
Akira Hatanaka
d3c031eb00 Reverse order of operands of address operand mem so that the base operand comes 
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
 2011-07-07 18:57:00 +00:00
Akira Hatanaka
31119a50bc Add missing return statement. 
llvm-svn: 134622
 2011-07-07 18:27:36 +00:00
Devang Patel
ff0a35a206 If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example, 
DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]

These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 

llvm-svn: 134620
 2011-07-07 17:45:33 +00:00
Joerg Sonnenberger
69f503e99c Recognize mipseb as alias for mips for symmetry with mipsel. 
llvm-svn: 134617
 2011-07-07 16:53:52 +00:00
Oscar Fuentes
835c073c59 Update CMake library dependencies 
llvm-svn: 134616
 2011-07-07 16:33:00 +00:00
Douglas Gregor
c21559842f Fix CMake build 
llvm-svn: 134614
 2011-07-07 15:59:22 +00:00
Cameron Zwarich
10c7a9fd7b The VMLA instruction and its friends are not actually fused; they're plain old 
multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609
 2011-07-07 08:28:52 +00:00
Evan Cheng
ac7afa4009 Sink feature IsThumb into MC layer. 
llvm-svn: 134608
 2011-07-07 08:26:46 +00:00
Evan Cheng
18acf2200c Compute feature bits at time of MCSubtargetInfo initialization. 
llvm-svn: 134606
 2011-07-07 07:07:08 +00:00
Chris Lattner
fb02989d86 type can be null 
llvm-svn: 134601
 2011-07-07 05:29:18 +00:00
Chris Lattner
a52824b79e use a more efficient check for 'is metadata' 
llvm-svn: 134599
 2011-07-07 05:12:37 +00:00
Bill Wendling
2b47bfeaa9 Use ArrayRef instead of a std::vector&. 
llvm-svn: 134595
 2011-07-07 04:42:01 +00:00
Lang Hames
9e52663aa4 Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The 
hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.

X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)

Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).

Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.

llvm-svn: 134592
 2011-07-07 04:31:51 +00:00
Evan Cheng
952943f744 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. 
llvm-svn: 134590
 2011-07-07 03:55:05 +00:00
Bill Wendling
ba39846c2b Add a target hook to encode the compact unwind information. 
llvm-svn: 134577
 2011-07-07 00:54:13 +00:00
Devang Patel
a30ca05040 Add DEBUG messages. 
llvm-svn: 134572
 2011-07-07 00:14:27 +00:00
Evan Cheng
9581f645b3 Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC. 
llvm-svn: 134569
 2011-07-07 00:08:19 +00:00
Devang Patel
4011cc12b8 Use DBG_VALUE location while inserting DBG_VALUE during alloca promotion. 
llvm-svn: 134568
 2011-07-07 00:05:58 +00:00
Jakub Staszak
7f9c0d5ac8 Fix a bug in the "expect" intrinsic lowering. 
llvm-svn: 134566
 2011-07-06 23:50:16 +00:00
Eli Friedman
293141407b When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). 
Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces.

<rdar://problem/9716278>

llvm-svn: 134565
 2011-07-06 23:41:48 +00:00
Devang Patel
94f4eec7e4 Remove dead code. 
llvm-svn: 134561
 2011-07-06 23:26:18 +00:00
Devang Patel
0abf331128 Typo. 
llvm-svn: 134559
 2011-07-06 23:09:51 +00:00
Bill Wendling
fd3f4e7040 Clean up the #includes. 
llvm-svn: 134557
 2011-07-06 22:52:32 +00:00
Eric Christopher
91acbb256c Grammar and 80-col. 
llvm-svn: 134555
 2011-07-06 22:41:18 +00:00
Devang Patel
47d505f9ef Handle cases where multiple dbg.declare and dbg.value intrinsics are tied to one alloca. 
llvm-svn: 134549
 2011-07-06 22:06:11 +00:00
Evan Cheng
5b5fb8c78b Add ARM MC registry routines. 
llvm-svn: 134547
 2011-07-06 22:02:34 +00:00
Evan Cheng
b0e0a318b7 Rename files for consistency. 
llvm-svn: 134546
 2011-07-06 22:01:53 +00:00
Jim Grosbach
9863be57e0 Mark ARM pseudo-instructions as isPseudo. 
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540
 2011-07-06 21:35:46 +00:00
Devang Patel
214fa1739f Simplify. Consolidate dbg.declare handling in AllocaPromoter. 
llvm-svn: 134538
 2011-07-06 21:09:55 +00:00