1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
Commit Graph

144 Commits

Author SHA1 Message Date
Nate Begeman
84be54b731 No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.

llvm-svn: 24541
2005-11-30 18:54:35 +00:00
Chris Lattner
fdc786b18f Fix a bug in a recent patch that broke shifts
llvm-svn: 24526
2005-11-30 05:11:18 +00:00
Evan Cheng
f412b7ba0c Add more X86 ISel patterns.
llvm-svn: 24520
2005-11-29 19:38:52 +00:00
Chris Lattner
5d9ecff961 encode rdtsc correctly
llvm-svn: 24435
2005-11-20 22:13:18 +00:00
Andrew Lenharth
a369904fc5 The second patch of X86 support for read cycle counter.
llvm-svn: 24430
2005-11-20 21:41:10 +00:00
Chris Lattner
af79013023 Teach the x86 backend about the register constraints of its addressing mode.
Patch by Evan Cheng

llvm-svn: 24423
2005-11-19 07:01:30 +00:00
Chris Lattner
72fa26a85b add more patterns, patch by Evan Cheng.
llvm-svn: 24406
2005-11-18 01:04:42 +00:00
Chris Lattner
f829636c6b Add patterns for some 16-bit immediate instructions, patch contributed by
Evan Cheng.

llvm-svn: 24384
2005-11-17 02:01:55 +00:00
Chris Lattner
fec54e57a0 Add patterns for several simple instructions that take i32 immediates.
Patch contributed by Evan Cheng!

llvm-svn: 24382
2005-11-16 22:59:19 +00:00
Nate Begeman
3b6c2df603 Properly split f32 and f64 into separate register classes for scalar sse fp
fixing a bunch of nasty hackery

llvm-svn: 23735
2005-10-14 22:06:00 +00:00
Chris Lattner
54139f0b83 give all operands names
llvm-svn: 23356
2005-09-14 21:10:24 +00:00
Chris Lattner
d7bd59d77e add a few missing cases
llvm-svn: 22891
2005-08-19 00:41:29 +00:00
Chris Lattner
f62a66a21c Give ADJCALLSTACKDOWN/UP the correct operands.
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.

llvm-svn: 22890
2005-08-19 00:38:22 +00:00
Nate Begeman
6cd034da8e Scalar SSE: load +0.0 -> xorps/xorpd
Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted

llvm-svn: 22637
2005-08-03 23:26:28 +00:00
Nate Begeman
957e0e7c9e Get closer to fully working scalar FP in SSE regs. This gets singlesource
working, and Olden/power.

llvm-svn: 22441
2005-07-15 00:38:55 +00:00
Nate Begeman
e5314eb2c2 First round of support for doing scalar FP using the SSE2 ISA extension and
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340
2005-07-06 18:59:04 +00:00
Nate Begeman
032a94775d Initial set of .td file changes necessary to get scalar fp in xmm registers
working.  The instruction selector changes will hopefully be coming later
this week once they are debugged.  This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87.  As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier.  This leads to significantly
better codegen in several cases.

llvm-svn: 22300
2005-06-27 21:20:31 +00:00
Chris Lattner
7327c042b4 Add markers in the asm file for tail calls, add a new ADJSTACKPTRri
sorta-pseudo-instruction

llvm-svn: 22042
2005-05-15 03:10:37 +00:00
Chris Lattner
64232a8480 Yes, calltarget is the operand of the day.
llvm-svn: 22040
2005-05-15 01:10:30 +00:00
Chris Lattner
37e226fa9b Add some new instructions
llvm-svn: 22036
2005-05-14 23:35:21 +00:00
Chris Lattner
83d7e55471 add 'ret imm' instruction
llvm-svn: 21945
2005-05-13 17:56:48 +00:00
Chris Lattner
7ba0699b05 Fix the syntax of the i/o instructions, these are obviously unused.
llvm-svn: 21829
2005-05-09 20:49:20 +00:00
Chris Lattner
236cef3563 Add some new X86 instrs, patch contributed by Morten Ofstad
llvm-svn: 21608
2005-04-28 21:50:05 +00:00
Chris Lattner
ba7cdbebb1 add signed versions of the extra precision multiplies
llvm-svn: 21106
2005-04-06 04:19:22 +00:00
Chris Lattner
71434aa2dd add an fabs instr
llvm-svn: 21006
2005-04-02 04:31:56 +00:00
Chris Lattner
a024984017 Fix spelling, patch contributed by Gabor Greif!
llvm-svn: 20343
2005-02-27 06:18:25 +00:00
Chris Lattner
34757ff939 Add rotate instructions.
llvm-svn: 19690
2005-01-19 07:50:03 +00:00
Chris Lattner
9d5ee289d7 Improve coverage of the X86 instruction set by adding 16-bit shift doubles.
llvm-svn: 19687
2005-01-19 07:31:24 +00:00
Chris Lattner
c03f360215 Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shld %EDX, %EDX, 2
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

Note the magically transmogrifying immediate.

llvm-svn: 19686
2005-01-19 07:11:01 +00:00
Chris Lattner
65d007ab62 Add conditional moves for the parity flag.
llvm-svn: 19437
2005-01-10 22:09:33 +00:00
Chris Lattner
1aaf8cccb2 ADC and IMUL are also commutable.
llvm-svn: 19264
2005-01-03 01:27:59 +00:00
Chris Lattner
0d6f03e52b Two changes here:
1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP.
2. Set the isCommutable and isPromotableTo3Address bits on several
   instructions.

llvm-svn: 19246
2005-01-02 02:35:46 +00:00
John Criswell
402e338f11 Correct the name of stosd for the AT&T syntax:
It's stosl (l for long == 32 bit).

llvm-svn: 17658
2004-11-10 04:48:15 +00:00
Chris Lattner
82aa8544a5 Remove debugging code, fix encoding problem. This fixes the problems
the JIT had last night.

llvm-svn: 16766
2004-10-06 14:31:50 +00:00
Chris Lattner
acd213fba3 Add some new instructions. Fix the asm string for sbb32rr
llvm-svn: 16759
2004-10-06 04:01:02 +00:00
Chris Lattner
5959f4a108 Convert some missed patterns to support AT&T style
llvm-svn: 16645
2004-10-04 07:23:07 +00:00
Chris Lattner
a05d9f53bb Apparently the GNU assembler has a HUGE hack to be compatible with really
old and broken AT&T syntax assemblers.  The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.

llvm-svn: 16644
2004-10-04 07:08:46 +00:00
Chris Lattner
08098895db Fix incorrect suffix
llvm-svn: 16642
2004-10-04 05:20:16 +00:00
Chris Lattner
c2fc9597bd Fix some more missed suffixes and swapped operands
llvm-svn: 16641
2004-10-04 01:38:10 +00:00
Chris Lattner
7b15a84728 Add missing suffixes to FP instructions for AT&T mode
llvm-svn: 16640
2004-10-04 00:43:31 +00:00
Chris Lattner
94780713a8 Add support to the instruction patterns for AT&T style output, which will
hopefully lead to the death of the 'GasBugWorkaroundEmitter'.  This also
includes changes to wrap the whole file to 80 columns! Woot! :)

Note that the AT&T style output has not been tested at all.

llvm-svn: 16638
2004-10-03 20:35:00 +00:00
Alkis Evlogimenos
4d2b0a2b5b Use a shorter form to express implicit use/defs in FpGETRESULT and
FpSETRESULT.

llvm-svn: 16247
2004-09-08 18:29:31 +00:00
Alkis Evlogimenos
3540de9ea6 A call instruction should implicitely define ST0 since the return
value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.

llvm-svn: 16246
2004-09-08 16:54:54 +00:00
Chris Lattner
5e7e9b6c26 Remove a bunch of ad-hoc target-specific flags that were only used by the
old asmprinter.

llvm-svn: 15660
2004-08-11 07:12:04 +00:00
Chris Lattner
3cef2f82ff Add asmprintergen support for the last X86 instruction that needs it: pcrelative calls.
llvm-svn: 15657
2004-08-11 06:59:12 +00:00
Chris Lattner
9c171be048 Scrunch memoperands, add a few more for floating point memops
Eliminate the FPI*m classes, converting them to use FPI instead.

llvm-svn: 15655
2004-08-11 06:50:10 +00:00
Chris Lattner
b287047c3f Make FPI take asm string and operand list
llvm-svn: 15653
2004-08-11 05:54:16 +00:00
Chris Lattner
c304bf7e03 Nuke the Im*i* patterns, by asmprintergenifying all users.
llvm-svn: 15652
2004-08-11 05:31:07 +00:00
Chris Lattner
65ab459759 X86 instructions that read-modify-write memory are not LLVM two-address instructions.
llvm-svn: 15651
2004-08-11 05:07:25 +00:00
Chris Lattner
384711a69c Get rid of the Im8, Im16, Im32 classes, converting more instructions over to
asmprintergeneration

llvm-svn: 15650
2004-08-11 04:31:00 +00:00