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Commit Graph

10768 Commits

Author SHA1 Message Date
Evan Cheng
84f06f0ee6 Enable cross register class coalescing.
llvm-svn: 76281
2009-07-18 02:10:10 +00:00
Evan Cheng
fe529a2c29 Revert 76177 for now. It's messing up ARM asm printing. Also this significant debate about its efficiency.
llvm-svn: 76279
2009-07-18 01:43:53 +00:00
Evan Cheng
67ccedff04 Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense.
llvm-svn: 76248
2009-07-17 22:13:25 +00:00
Chris Lattner
ffe0c407be Untangle a snarl that I discovered when updating the mangler,
starting in getCurrentFunctionEHName.  Among other problems,
we would try to privative a "foo.eh" label, but end up emitting
the label as _Lfoo.eh instead of L_foo.eh on darwin.  This is really
bad, and the linker has always tolerated these labels existing.
For now, just emit them as _foo.eh.

This patch also fixes problems with ".eh" labels on unnamed
functions and eliminates two strangely defined TargetAsmInfo
hooks.

llvm-svn: 76231
2009-07-17 20:46:40 +00:00
Daniel Dunbar
de011196a4 Sketch support for target specific assembly parser.
- Not fully enabled yet, need a configure regeneration.

llvm-svn: 76230
2009-07-17 20:42:00 +00:00
Daniel Dunbar
cff1fabab5 Start generating AsmMatcher.inc for X86.
llvm-svn: 76213
2009-07-17 18:55:26 +00:00
Jeffrey Yasskin
1669f312b5 r76102 added the MachineCodeEmitter::processDebugLoc call and called it from
the X86 Emitter.  This patch extends that to the rest of the targets that can
write to a MachineCodeEmitter: ARM, Alpha, and PPC.

llvm-svn: 76211
2009-07-17 18:49:39 +00:00
Anton Korobeynikov
fbac44c040 Add missed return
llvm-svn: 76209
2009-07-17 18:28:59 +00:00
David Greene
70e8a51127 Add logic to align instruction operands to columns for pretty-printing.
No target uses this currently.  This patch only adds the mechanism so
that local installations can choose to enable this.

llvm-svn: 76177
2009-07-17 14:24:46 +00:00
Duncan Sands
d1b273609e Avoid a compiler warning when assertions are turned off.
llvm-svn: 76176
2009-07-17 12:25:14 +00:00
Eli Friedman
6e61f56a5c Oops, accidentally set a legal operation to expand.
llvm-svn: 76165
2009-07-17 07:34:23 +00:00
Eli Friedman
b946eb988f Expand misc operations from test/CodeGen/Generic.
llvm-svn: 76163
2009-07-17 07:28:06 +00:00
Eli Friedman
93d9c9f85f Handle void in XCoreTargetLowering::isLegalAddressingMode. Triggers in
test/CodeGen/Generic.

llvm-svn: 76162
2009-07-17 07:16:38 +00:00
Eli Friedman
7c72917709 Remove some unnecessary expansion markings. Add a few expansion
markings that show up in test/CodeGen/Generic.

llvm-svn: 76160
2009-07-17 07:03:00 +00:00
Eli Friedman
98a65107b3 Add operation expansion/promotion for a bunch of operations, many of
which show up in test/CodeGen/Generic.

llvm-svn: 76158
2009-07-17 06:36:24 +00:00
Evan Cheng
490d2cc5a4 Fix tSUBspi operand definition. It reads and writes sp, which is a high register.
llvm-svn: 76155
2009-07-17 05:43:12 +00:00
Eli Friedman
12bf15280b Set an operation expansion, noticed while running
llc over test/CodeGen/Generic with -march=alpha.

llvm-svn: 76154
2009-07-17 05:23:03 +00:00
Eli Friedman
6be9680238 One more operation expansion for MIPS, from test/CodeGen/Generic.
llvm-svn: 76149
2009-07-17 04:07:24 +00:00
Daniel Dunbar
f988544dcf Make sure CWriter's Context get's initialized.
llvm-svn: 76147
2009-07-17 03:43:21 +00:00
Eli Friedman
48510f16fb Expand a bunch of illegal operations on MIPS (found by
inspection and running over CodeGen/Generic).

llvm-svn: 76146
2009-07-17 02:28:12 +00:00
Daniel Dunbar
fd7e588f92 Fix 'may be used uninitialized' warning.
- Anton, please review.

llvm-svn: 76144
2009-07-17 02:19:26 +00:00
Anton Korobeynikov
dc39f4fff8 Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.

llvm-svn: 76124
2009-07-16 23:26:06 +00:00
Evan Cheng
e9dc6cf3b1 GV with ghost linkage (module being lazily streamed in in JIT lazy compilation mode) do not require extra load from stub. This fixes ExecutionEngine/2005-12-02-TailCallBug.ll.
llvm-svn: 76121
2009-07-16 22:53:10 +00:00
Jakob Stoklund Olesen
c438f0ecfa Silence warning in Linux builds:
X86InstrInfo.cpp:2272: warning: suggest explicit braces to avoid ambiguous 'else'

llvm-svn: 76105
2009-07-16 21:24:13 +00:00
Jeffrey Yasskin
a4b7ea7485 Add line numbers to OProfile. To do this, I added a processDebugLoc()
call to the MachineCodeEmitter interface and made copying the start
line of a function not conditional on whether we're emitting Dwarf
debug information. I'll propagate the processDebugLoc() calls to the
non-X86 targets in a followup patch.

In the long run, it'll probably be better to gather this information
through the DwarfWriter, but the DwarfWriter currently depends on the
AsmPrinter and TargetAsmInfo, and fixing that would be out of the way
for this patch.

There's a bug in OProfile 0.9.4 that makes it ignore line numbers for
addresses above 4G, and a patch fixing it at
http://thread.gmane.org/gmane.linux.oprofile/7634

Sample output:

$ sudo opcontrol --reset; sudo opcontrol --start-daemon; sudo opcontrol --start; `pwd`/Debug/bin/lli fib.bc; sudo opcontrol --stop
Signalling daemon... done
Profiler running.
fib(40) == 165580141
Stopping profiling.

$ opreport -g -d -l `pwd`/Debug/bin/lli|head -60
Overflow stats not available
CPU: Core 2, speed 1998 MHz (estimated)
Counted CPU_CLK_UNHALTED events (Clock cycles when not halted) with a unit mask of 0x00 (Unhalted core cycles) count 100000
vma      samples  %        linenr info                 image name               symbol name
00007f67a30370b0 25489    61.2554  fib.c:24                    10946.jo                 fib_left
  00007f67a30370b0 1634      6.4106  fib.c:24
  00007f67a30370b1 83        0.3256  fib.c:24
  00007f67a30370b9 1997      7.8348  fib.c:24
  00007f67a30370c6 2080      8.1604  fib.c:27
  00007f67a30370c8 988       3.8762  fib.c:27
  00007f67a30370cd 1315      5.1591  fib.c:27
  00007f67a30370cf 251       0.9847  fib.c:27
  00007f67a30370d3 1191      4.6726  fib.c:27
  00007f67a30370d6 975       3.8252  fib.c:27
  00007f67a30370db 1010      3.9625  fib.c:27
  00007f67a30370dd 242       0.9494  fib.c:27
  00007f67a30370e1 2782     10.9145  fib.c:28
  00007f67a30370e5 3768     14.7828  fib.c:28
  00007f67a30370eb 615       2.4128  (no location information)
  00007f67a30370f3 6558     25.7287  (no location information)
00007f67a3037100 15603    37.4973  fib.c:29                    10946.jo                 fib_right
  00007f67a3037100 1646     10.5493  fib.c:29
  00007f67a3037101 45        0.2884  fib.c:29
  00007f67a3037109 2372     15.2022  fib.c:29
  00007f67a3037116 2234     14.3178  fib.c:32
  00007f67a3037118 612       3.9223  fib.c:32
  00007f67a303711d 622       3.9864  fib.c:32
  00007f67a303711f 385       2.4675  fib.c:32
  00007f67a3037123 404       2.5892  fib.c:32
  00007f67a3037126 634       4.0633  fib.c:32
  00007f67a303712b 870       5.5759  fib.c:32
  00007f67a303712d 62        0.3974  fib.c:32
  00007f67a3037131 1848     11.8439  fib.c:33
  00007f67a3037135 2840     18.2016  fib.c:33
  00007f67a303713a 1         0.0064  fib.c:33
  00007f67a303713b 1023      6.5564  (no location information)
  00007f67a3037143 5         0.0320  (no location information)
000000000080c1e4 15        0.0360  MachineOperand.h:150        lli                      llvm::MachineOperand::isReg() const
  000000000080c1e4 6        40.0000  MachineOperand.h:150
  000000000080c1ec 2        13.3333  MachineOperand.h:150
...

llvm-svn: 76102
2009-07-16 21:07:26 +00:00
Evan Cheng
39e5f6205a With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction.
llvm-svn: 76094
2009-07-16 18:44:05 +00:00
Anton Korobeynikov
c66cf22284 Unbreak
llvm-svn: 76064
2009-07-16 14:36:52 +00:00
Anton Korobeynikov
3e8bb65ec8 Temporary disable 16 bit bswap
llvm-svn: 76063
2009-07-16 14:35:57 +00:00
Anton Korobeynikov
94e21c8740 Add instruction formats and few opcodes
llvm-svn: 76062
2009-07-16 14:35:20 +00:00
Anton Korobeynikov
e11a89ba74 Add bswap patterns
llvm-svn: 76061
2009-07-16 14:34:52 +00:00
Anton Korobeynikov
6c622a4547 Provide crazy pseudos for regpairs spills / reloads
llvm-svn: 76060
2009-07-16 14:34:15 +00:00
Anton Korobeynikov
c5e948c021 Handle long-disp stuff more consistently
llvm-svn: 76059
2009-07-16 14:33:52 +00:00
Anton Korobeynikov
d9c48cfd00 All FP instructions have 12 bit memory displacement field
llvm-svn: 76058
2009-07-16 14:33:27 +00:00
Anton Korobeynikov
e1bf81893d Another predicate routine
llvm-svn: 76057
2009-07-16 14:33:01 +00:00
Anton Korobeynikov
605ebc2c3c More helpers
llvm-svn: 76056
2009-07-16 14:32:41 +00:00
Anton Korobeynikov
014ce79e73 Add bunch of branch folding stuff
llvm-svn: 76055
2009-07-16 14:32:19 +00:00
Anton Korobeynikov
918a93419c Add missed opcodes to short => long displacement conversion
llvm-svn: 76054
2009-07-16 14:31:52 +00:00
Anton Korobeynikov
08d9f6b882 Cleanup
llvm-svn: 76053
2009-07-16 14:31:32 +00:00
Anton Korobeynikov
94f250ff30 Fix logic inversion for RI-mode address selection
llvm-svn: 76052
2009-07-16 14:31:14 +00:00
Anton Korobeynikov
373515d99e Expand 32-bit bitconverts via memory
llvm-svn: 76050
2009-07-16 14:30:29 +00:00
Anton Korobeynikov
080bdae588 Fix incomin arg stack frame offset in case we need to generate stack frame
llvm-svn: 76049
2009-07-16 14:29:57 +00:00
Anton Korobeynikov
c84e2bb30e Fix instruction mnemonics for some fp_to_sint operations
llvm-svn: 76048
2009-07-16 14:29:26 +00:00
Anton Korobeynikov
74497b2190 i32 values are passed extended also on stack. Handle this in generic way
llvm-svn: 76047
2009-07-16 14:29:05 +00:00
Anton Korobeynikov
319dc4e8d3 We definitely have 1-0 bools
llvm-svn: 76046
2009-07-16 14:28:46 +00:00
Anton Korobeynikov
2e8f54d16d Revert the commit, it just hides the real bug
llvm-svn: 76045
2009-07-16 14:28:26 +00:00
Anton Korobeynikov
0276bc9176 Out GR128 regclass is not a 'real' i128 one.
llvm-svn: 76044
2009-07-16 14:27:53 +00:00
Anton Korobeynikov
690fef7849 Add missed condbranch opcodes
llvm-svn: 76043
2009-07-16 14:27:26 +00:00
Anton Korobeynikov
4181716247 Handle bitconverts
llvm-svn: 76042
2009-07-16 14:27:01 +00:00
Anton Korobeynikov
60427c0b64 Unbreak mvi and friends - emit only 'significant' part of the operand
llvm-svn: 76041
2009-07-16 14:26:38 +00:00
Anton Korobeynikov
ff6d84fd85 Expand fp_to_uint too
llvm-svn: 76040
2009-07-16 14:26:06 +00:00