Jim Grosbach
86ecfda983
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
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the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
Jim Grosbach
1d5b71b3cc
Trailing whitespace
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llvm-svn: 117496
2010-10-27 21:39:08 +00:00
Jim Grosbach
4d4caf1384
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
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rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
Jim Grosbach
30f6744f05
First part of refactoring ARM addrmode2 (load/store) instructions to be more
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explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
Eric Christopher
0dab5810aa
Move rejection of NEON parameters earlier in fast isel call processing,
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note that we can actually handle some f64 arguments.
llvm-svn: 117209
2010-10-23 09:37:17 +00:00
Evan Cheng
e5b7a3a09f
Silence compiler warnings.
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llvm-svn: 117128
2010-10-22 18:57:05 +00:00
Eric Christopher
58a6e62c08
Add some basic ret instruction support to arm fast-isel.
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llvm-svn: 117085
2010-10-22 01:28:00 +00:00
Eric Christopher
59683c9d71
These don't need to be virtual.
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llvm-svn: 117068
2010-10-21 21:47:51 +00:00
Eric Christopher
7ded7e88c8
Handle storing args to the stack for calls.
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llvm-svn: 117055
2010-10-21 20:09:54 +00:00
Eric Christopher
b15029ea7e
More load/store refactoring, call reg+offset simplification from within
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the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
llvm-svn: 117051
2010-10-21 19:40:30 +00:00
Eric Christopher
7989939d87
Custom lower f64 args passed in integer registers.
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llvm-svn: 116977
2010-10-21 00:01:47 +00:00
Eric Christopher
78c7e84ce5
Fix a TODO by removing some unnecesary copies.
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llvm-svn: 116915
2010-10-20 08:02:24 +00:00
Eric Christopher
5850afe5f2
Revert r116220 - thus turning arm fast isel back on by default.
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llvm-svn: 116762
2010-10-18 22:53:53 +00:00
Eric Christopher
e453bd6697
Remove the check for invalid calling conventions. Testing shows that they're
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working just fine.
llvm-svn: 116698
2010-10-18 06:49:12 +00:00
Eric Christopher
6287738105
Lift arg promotion from the X86 backend. This should be unified at some point.
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llvm-svn: 116694
2010-10-18 02:17:53 +00:00
Eric Christopher
79c2206640
Now that we handle all allocas via a non-SP reg offset remove all of the
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special case handling for ARM::SP.
llvm-svn: 116688
2010-10-17 11:08:44 +00:00
Eric Christopher
d99f79f92b
Allow more load types to be materialized through the allocas.
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llvm-svn: 116683
2010-10-17 06:07:26 +00:00
Eric Christopher
5fcaab5d0e
Optimize GEP off of intermediate allocas.
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llvm-svn: 116681
2010-10-17 01:51:42 +00:00
Eric Christopher
20bbcbeceb
Fix comment.
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llvm-svn: 116680
2010-10-17 01:42:53 +00:00
Eric Christopher
d9b4b47b9a
Turn on AddOperator folding in GEP.
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llvm-svn: 116679
2010-10-17 01:41:46 +00:00
Eric Christopher
490f82bc32
Use the i12 immediate versions of the load instructions - they're handled
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more in the post-passes.
llvm-svn: 116678
2010-10-17 01:40:27 +00:00
Eric Christopher
98c6ce755a
Fix some funky formatting that got through.
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llvm-svn: 116653
2010-10-16 01:10:35 +00:00
Eric Christopher
69eaf30a42
Make sure offset is 0 for load/store register to the stack call.
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llvm-svn: 116640
2010-10-15 23:07:10 +00:00
Eric Christopher
7f8c3dff07
Fix else if -> if in store machinery.
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llvm-svn: 116628
2010-10-15 22:32:37 +00:00
Eric Christopher
a875589580
Refactor ARM fast-isel reg + offset to be a base + offset.
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llvm-svn: 116622
2010-10-15 21:32:12 +00:00
Eric Christopher
b287ab82d7
Expand GEP handling for constant offsets.
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llvm-svn: 116594
2010-10-15 18:02:07 +00:00
Eric Christopher
9060ac1be3
Handle more complex GEP based loads and add a few TODOs to deal with
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GEP + alloca.
llvm-svn: 116474
2010-10-14 09:29:41 +00:00
Jim Grosbach
506b966b9d
A few 80 column fixes.
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llvm-svn: 116451
2010-10-13 23:34:31 +00:00
Eric Christopher
19be5bd87c
Update comment.
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llvm-svn: 116438
2010-10-13 21:41:51 +00:00
Eric Christopher
f7ab2cd3df
Start handling more global variables.
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llvm-svn: 116401
2010-10-13 09:11:46 +00:00
Eric Christopher
af5b22e150
Fix thinko in arm fast isel alloca rewrite.
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llvm-svn: 116339
2010-10-12 21:23:43 +00:00
Eric Christopher
0763cc04c5
Rework alloca handling so that we can load or store from casted
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address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
llvm-svn: 116296
2010-10-12 05:39:06 +00:00
Eric Christopher
8789aa8799
Handle a wider arrangement of loads.
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llvm-svn: 116284
2010-10-12 00:43:21 +00:00
Eric Christopher
e1574aa60a
Use a sane mechanism for that assert.
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llvm-svn: 116249
2010-10-11 22:01:22 +00:00
Eric Christopher
926a41a84b
We're not going to handle dynamic allocas anywhere else.
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llvm-svn: 116240
2010-10-11 21:37:35 +00:00
Eric Christopher
cac7b248c7
Make sure that the call stack adjustments have default operands. Also
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leave custom lowerings for later.
Fixes some nightly tests.
llvm-svn: 116232
2010-10-11 21:20:02 +00:00
Eric Christopher
fa961e31b1
Found a bug turning this on by default. Disable again for now.
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llvm-svn: 116220
2010-10-11 20:26:21 +00:00
Eric Christopher
ff35a1f090
Fix help text.
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llvm-svn: 116218
2010-10-11 20:15:02 +00:00
Eric Christopher
b1a93706f7
Change flag from Enable to Disable since we're enabled by default.
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Also don't use fast-isel on non-darwin since it's untested.
llvm-svn: 116217
2010-10-11 20:05:22 +00:00
Eric Christopher
52c102fef0
Turn on arm fast isel by default.
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llvm-svn: 116212
2010-10-11 18:48:18 +00:00
Eric Christopher
019eeb9c55
Copy and pasteo.
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llvm-svn: 116198
2010-10-11 08:40:05 +00:00
Eric Christopher
a412d25090
Whitespace cleanup in ARM fast isel.
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llvm-svn: 116197
2010-10-11 08:38:55 +00:00
Eric Christopher
c100a052eb
Add srem libcall support to ARM fast isel.
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llvm-svn: 116196
2010-10-11 08:37:26 +00:00
Eric Christopher
af5baa8a0f
Add i8 sdiv support for ARM fast isel.
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llvm-svn: 116195
2010-10-11 08:31:54 +00:00
Eric Christopher
6f65f8a4d3
Implement select handling for ARM fast-isel.
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llvm-svn: 116194
2010-10-11 08:27:59 +00:00
Eric Christopher
a1d180e00e
Fix the store part of this as well. Fixes smg2000.
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llvm-svn: 116123
2010-10-08 23:52:16 +00:00
Eric Christopher
45a5ff5ca3
Move to thumb2 loads, fixes a problem with incoming registers
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as thumb1.
Fixes lencod.
llvm-svn: 116027
2010-10-08 01:13:17 +00:00
Eric Christopher
183b18d430
Remember to promote load/store types for stack to register size.
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llvm-svn: 115984
2010-10-07 21:40:18 +00:00
Eric Christopher
3a068c4252
Use the correct register class for load instructions - fixes
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compilation of MultiSource/Benchmarks/Bullet.
llvm-svn: 115907
2010-10-07 05:50:44 +00:00
Eric Christopher
b3e9588644
Use the correct register class here.
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llvm-svn: 115906
2010-10-07 05:39:19 +00:00