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Commit Graph

12 Commits

Author SHA1 Message Date
Evan Cheng
c9f31ae969 When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
llvm-svn: 77642
2009-07-30 23:29:25 +00:00
Chris Lattner
18af1b233a Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.

llvm-svn: 77501
2009-07-29 20:31:52 +00:00
Evan Cheng
b740190d2e - More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
2009-07-28 05:48:47 +00:00
Evan Cheng
d555fec28c Refactor. Get rid of a few more getOpcode() calls.
llvm-svn: 77164
2009-07-26 18:55:14 +00:00
David Goodwin
85bcdffa4f Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
llvm-svn: 76919
2009-07-24 00:16:18 +00:00
David Goodwin
f3c839e0b9 Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
llvm-svn: 76883
2009-07-23 17:06:46 +00:00
Evan Cheng
005330f8a0 Get rid one of the getRegisterNumbering. Also add D16 - D31.
llvm-svn: 76725
2009-07-22 05:55:18 +00:00
Evan Cheng
7a6b20df7f Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900
2009-07-16 09:20:10 +00:00
Evan Cheng
5bdb67db63 80 col violation.
llvm-svn: 75212
2009-07-10 00:45:16 +00:00
David Goodwin
94209a4c31 Generalize opcode selection in ARMBaseRegisterInfo.
llvm-svn: 75036
2009-07-08 20:28:28 +00:00
David Goodwin
c571c4b457 Push methods into base class in preparation for sharing.
llvm-svn: 75020
2009-07-08 18:31:39 +00:00
David Goodwin
7b4570ee1d Start breaking out common base functionality for register info.
llvm-svn: 75016
2009-07-08 17:28:55 +00:00