Craig Topper
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f68d77215d
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Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
llvm-svn: 138034
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2011-08-19 05:28:50 +00:00 |
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Eli Friedman
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f6cac8a620
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Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
llvm-svn: 135337
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2011-07-16 02:41:28 +00:00 |
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Sean Callanan
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e78b505311
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Basic sanity checks to ensure that 2- and 3-byte
VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
llvm-svn: 127647
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2011-03-15 01:32:46 +00:00 |
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Sean Callanan
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e1308394f1
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Fixed a bug in the enhanced disassembler that caused
it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
llvm-svn: 126302
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2011-02-23 03:31:28 +00:00 |
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Sean Callanan
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419a1b871e
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Added a testcase for the enhanced disassembly bug
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.
llvm-svn: 126182
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2011-02-22 02:19:18 +00:00 |
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Rafael Espindola
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64814fff0b
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Correctly disassemble truncated asm.
Patch by Richard Simth.
llvm-svn: 122962
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2011-01-06 16:48:42 +00:00 |
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Dale Johannesen
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05a7c613fa
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Segregate tests by target.
llvm-svn: 119050
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2010-11-14 18:14:32 +00:00 |
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