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87f9c41b1c
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22181 Commits

Author SHA1 Message Date
Roman Divacky
87f9c41b1c Specify MachinePointerInfo as refering to the argument value and offset of the 
store when handling byval arguments. Thus preventing reordering of the store
with load with post-RA scheduler.

llvm-svn: 164553
 2012-09-24 20:47:19 +00:00
Chad Rosier
599b467187 Rather then have a wrapper function, have tblgen instantiate the implementation. 
llvm-svn: 164548
 2012-09-24 19:32:29 +00:00
NAKAMURA Takumi
8377e86232 ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable] 
llvm-svn: 164459
 2012-09-22 13:12:28 +00:00
NAKAMURA Takumi
79a8490f7a Whitespace. 
llvm-svn: 164458
 2012-09-22 13:12:22 +00:00
Tim Northover
7cab153d37 Fix edge cases of ARM shift operands in arith instructions. 
As before with load instructions, oddities like "asr #32", "rrx" could
be printed incorrectly.

Patch by Chris Lidbury.

llvm-svn: 164456
 2012-09-22 11:18:19 +00:00
Tim Northover
1c60305666 Fix the handling of edge cases in ARM shifted operands. 
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

llvm-svn: 164455
 2012-09-22 11:18:12 +00:00
Michael Liao
3d9c40c0c8 Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#' 
llvm-svn: 164453
 2012-09-22 05:41:15 +00:00
Michael Liao
0a4f3eefaf Fix typo in r164357 
llvm-svn: 164452
 2012-09-22 03:39:42 +00:00
Akira Hatanaka
cf8158381d MIPS DSP: Add immediate leaves. 
llvm-svn: 164435
 2012-09-22 00:07:12 +00:00
Akira Hatanaka
e8ffbb3ace MIPS DSP: Add predicates and instruction template. 
llvm-svn: 164434
 2012-09-22 00:06:06 +00:00
Akira Hatanaka
4acf68deb2 Add MIPS DSP register classes. Set actions of DSP vector operations and override 
TargetLowering's callback functions.

llvm-svn: 164431
 2012-09-21 23:58:31 +00:00
Akira Hatanaka
5ead4f3d78 SelectionDAG node enums for MIPS DSP nodes. 
llvm-svn: 164430
 2012-09-21 23:52:47 +00:00
Akira Hatanaka
00202df6d5 Add MIPS accumulator and DSP control registers. 
llvm-svn: 164429
 2012-09-21 23:48:37 +00:00
Akira Hatanaka
d89661f8bd Add flags and feature bits for mips dsp. 
llvm-svn: 164428
 2012-09-21 23:41:49 +00:00
Chad Rosier
fd5e542cea [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser. 
llvm-svn: 164420
 2012-09-21 22:21:26 +00:00
Chad Rosier
bfd7fc3e7e Add comment. 
llvm-svn: 164415
 2012-09-21 21:08:46 +00:00
Chad Rosier
2cc6afaac6 Add comment. 
llvm-svn: 164414
 2012-09-21 20:51:43 +00:00
Chad Rosier
a58913fc00 [fast-isel] Fallback to SelectionDAG isel if we require strict alignment for 
non-aligned i32 loads/stores.
rdar://12304911

llvm-svn: 164381
 2012-09-21 16:58:35 +00:00
Michael Liao
9a17cba52b Fix a typo in r164357 
llvm-svn: 164372
 2012-09-21 16:03:03 +00:00
Bill Wendling
38bffadcad Make the 'get*AlignmentFromAttr' functions into member functions within the Attributes class. Now with fix. 
llvm-svn: 164370
 2012-09-21 15:26:31 +00:00
Andrew Trick
2545253eda Cortex-A9 latency fixes (w/ -schedmodel only). 
Quick review against the manual revealed a few obvious mistakes.

llvm-svn: 164361
 2012-09-21 05:06:40 +00:00
Michael Liao
2197b133f8 Add missing i8 max/min/umax/umin support 
- Fix PR5145 and turn on test 8-bit atomic ops

llvm-svn: 164358
 2012-09-21 03:18:52 +00:00
Michael Liao
439a9cea68 Revise td of X86 atomic instructions 
- Rewirte most atomic instructions in templates for both better
  maintenance and future extensions, such as HLE in TSX.

llvm-svn: 164357
 2012-09-21 03:00:17 +00:00
NAKAMURA Takumi
6900d8a214 Mips16FrameLowering.cpp: Remove unused TII introduced in r164349. [-Wunused-variable] 
llvm-svn: 164354
 2012-09-21 02:21:30 +00:00
Akira Hatanaka
39d54479a3 Properly save and restore RA and Mips16 callee save registers S0,S1 
Patch by Reed Kotler.

llvm-svn: 164349
 2012-09-21 01:08:16 +00:00
Chad Rosier
8a1b0217f6 [fast-isel] Fallback to SelectionDAG isel if we require strict alignment for 
non-halfword-aligned i16 loads/stores.
rdar://12304911

llvm-svn: 164345
 2012-09-21 00:41:42 +00:00
Jim Grosbach
cfecc18fc8 Tidy up. Whitespace. 
llvm-svn: 164344
 2012-09-21 00:36:42 +00:00
Jim Grosbach
8293ae4ed7 Tidy up. Formatting. 
llvm-svn: 164343
 2012-09-21 00:26:53 +00:00
Jim Grosbach
135898ebe3 ARM: Use a dedicated intrinsic for vector bitwise select. 
The expression based expansion too often results in IR level optimizations
splitting the intermediate values into separate basic blocks, preventing
the formation of the VBSL instruction as the code author intended. In
particular, LICM would often hoist part of the computation out of a loop.

rdar://11011471

llvm-svn: 164340
 2012-09-21 00:18:20 +00:00
Bill Wendling
65a9731d9c Revert r164308 to fix buildbots. 
llvm-svn: 164309
 2012-09-20 16:59:57 +00:00
Bill Wendling
89e5c2d955 Make the 'get*AlignmentFromAttr' functions into member functions within the Attributes class. 
llvm-svn: 164308
 2012-09-20 16:27:05 +00:00
Craig Topper
2eb5a713a8 Change enum type in a static table to uint8_t instead. Saves about 700 hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness. 
llvm-svn: 164285
 2012-09-20 06:14:08 +00:00
Michael Liao
34658dca78 Re-work X86 code generation of atomic ops with spin-loop 
- Rewrite/merge pseudo-atomic instruction emitters to address the
  following issue:
  * Reduce one unnecessary load in spin-loop

    previously the spin-loop looks like

        thisMBB:
        newMBB:
          ld  t1 = [bitinstr.addr]
          op  t2 = t1, [bitinstr.val]
          not t3 = t2  (if Invert)
          mov EAX = t1
          lcs dest = [bitinstr.addr], t3  [EAX is implicit]
          bz  newMBB
          fallthrough -->nextMBB

    the 'ld' at the beginning of newMBB should be lift out of the loop
    as lcs (or CMPXCHG on x86) will load the current memory value into
    EAX. This loop is refined as:

        thisMBB:
          EAX = LOAD [MI.addr]
        mainMBB:
          t1 = OP [MI.val], EAX
          LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
          JNE mainMBB
        sinkMBB:

  * Remove immopc as, so far, all pseudo-atomic instructions has
    all-register form only, there is no immedidate operand.

  * Remove unnecessary attributes/modifiers in pseudo-atomic instruction
    td

  * Fix issues in PR13458

- Add comprehensive tests on atomic ops on various data types.
  NOTE: Some of them are turned off due to missing functionality.

- Revise tests due to the new spin-loop generated.

llvm-svn: 164281
 2012-09-20 03:06:15 +00:00
Michael Liao
2730b7865e Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArith 
- Merge the processing of LOAD_ADD with other atomic load-arith
  operations
- Separate the logic getting target constant for atomic-load-op and add
  an optimization for atomic-load-add on i16 with negative value
- Optimize a minor case for atomic-fetch-add i16 with negative operand. Test
  case is revised.

llvm-svn: 164243
 2012-09-19 19:36:58 +00:00
Bill Schmidt
4e7e64ff70 Small structs for PPC64 SVR4 must be passed right-justified in registers. 
lib/Target/PowerPC/PPCISelLowering.{h,cpp}
 Rename LowerFormalArguments_Darwin to LowerFormalArguments_Darwin_Or_64SVR4.
 Rename LowerFormalArguments_SVR4 to LowerFormalArguments_32SVR4.
 Receive small structs right-justified in LowerFormalArguments_Darwin_Or_64SVR4.
 Rename LowerCall_Darwin to LowerCall_Darwin_Or_64SVR4.
 Rename LowerCall_SVR4 to LowerCall_32SVR4.
 Pass small structs right-justified in LowerCall_Darwin_Or_64SVR4.

test/CodeGen/PowerPC/structsinregs.ll
 New test.

llvm-svn: 164228
 2012-09-19 15:42:13 +00:00
Craig Topper
abbf768c15 Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
llvm-svn: 164204
 2012-09-19 06:37:45 +00:00
Craig Topper
7c37abcace Add explicit VEX_L tags to all 256-bit instructions. This will allow us to remove code from the code emitters that examined operands to set the L-bit. 
llvm-svn: 164202
 2012-09-19 06:06:34 +00:00
Evan Cheng
1a3416521f MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648 
llvm-svn: 164169
 2012-09-18 21:24:16 +00:00
Roman Divacky
748e9dfd91 Fix the isLocalCall() by checking for linker weakness as well. 
llvm-svn: 164155
 2012-09-18 18:27:49 +00:00
Akira Hatanaka
a1ab530be9 Revert r164051. 
llvm-svn: 164150
 2012-09-18 18:08:25 +00:00
Roman Divacky
bb7740900c Avoid symbol name clash when filling TOC. 
Patch by Adhemerval Zanella.

llvm-svn: 164141
 2012-09-18 17:10:37 +00:00
Roman Divacky
377f342a56 On PPC64 emit the environment pointer. Patch by Adhemerval Zanella. 
llvm-svn: 164139
 2012-09-18 16:55:29 +00:00
Roman Divacky
953cd43dfa Optimize local func calls to not emit nop for TOC restoration. 
Patch by Adhemerval Zanella.

llvm-svn: 164138
 2012-09-18 16:47:58 +00:00
Roman Divacky
e91b4521bf When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend 
store this and use it to not emit long nops when the CPU is geode which
doesnt support them.

Fixes PR11212.

llvm-svn: 164132
 2012-09-18 16:08:49 +00:00
James Molloy
4cb3751b3e More domain conversion; convert VFP VMOVS to NEON instructions in more cases - when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not. 
llvm-svn: 164114
 2012-09-18 08:31:15 +00:00
Andrew Trick
65c7aae93f TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
llvm-svn: 164092
 2012-09-18 03:18:56 +00:00
Evan Cheng
82c85585f9 Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte 
aligned address. Based on patch by David Peixotto.

Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment
hints. rdar://12090772, rdar://12238782

llvm-svn: 164089
 2012-09-18 01:42:45 +00:00
Andrew Trick
150c97940b Revert r164061-r164067. Most of the new subtarget emitter. 
I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072
 2012-09-17 23:00:42 +00:00
Andrew Trick
8a499d1f62 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
llvm-svn: 164061
 2012-09-17 22:18:55 +00:00
Jan Wen Voung
bd8575d1d7 Add some cases to x86 OptimizeCompare to handle DEC and INC, too. 
While we are setting the earlier def to true, also make it live.

llvm-svn: 164056
 2012-09-17 22:04:23 +00:00