1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Commit Graph

139127 Commits

Author SHA1 Message Date
Mehdi Amini
885692c663 ThinLTO: don't perform incremental LTO on module without a hash
Clang always emit a hash for ThinLTO, but as other frontend are
starting to use ThinLTO, this could be a serious bug.

Differential Revision: https://reviews.llvm.org/D25379

llvm-svn: 283655
2016-10-08 04:44:23 +00:00
Mehdi Amini
e74b55c5f5 ThinLTO: handles modules with empty summaries
We need to add an entry in the combined-index for modules that have
a hash but otherwise empty summary, this is needed so that we can
get the hash for the module.

Also, if no entry is present in the combined index for a module, we
need to skip it when trying to compute a cache entry.

Differential Revision: https://reviews.llvm.org/D25300

llvm-svn: 283654
2016-10-08 04:44:18 +00:00
Mehdi Amini
f42afd26c3 Requires the AVR backend for running test/CodeGen/AVR
llvm-svn: 283653
2016-10-08 04:39:34 +00:00
Kyle Butt
db90994d08 Revert "Codegen: Tail-duplicate during placement."
This reverts commit 71c312652c10f1855b28d06697c08d47e7a243e4.

llvm-svn: 283647
2016-10-08 01:47:05 +00:00
Dylan McKay
7daf0ee243 [AVR] Add backend dependencies to MCTargetDesc/LLVMBuild.txt
llvm-svn: 283642
2016-10-08 01:14:23 +00:00
Zachary Turner
6931521bfe [pdb] Dump Module Symbols to Yaml.
This is the first step towards round-tripping symbol information,
and thusly being able to write symbol information to a PDB.

This patch writes the symbol information for each compiland to
the Yaml when running in pdb2yaml mode.  There's still some loose
ends, such as what to do about relocations (necessary in order to
print linkage names), how to print enums with friendly names, and
how to give the dumper access to the StringTable, but this is a
good first start.

llvm-svn: 283641
2016-10-08 01:12:01 +00:00
Dylan McKay
6ea48bea7f Fix incorrect assertion in AVRFrameLowering.cpp
This wasn't looking at the right instruction, and would always fail.

llvm-svn: 283640
2016-10-08 01:10:36 +00:00
Dylan McKay
729f814148 [AVR] Don't worry about call frame size when initializing frame pointer
We previously only used the frame pointer if the frame pointer was too
big. This was to work around a bug (described in this old commit)

https://sourceforge.net/p/avr-llvm/code/204/tree//llvm/trunk/AVR/AVRFrameLowering.cpp?diff=50d64d912718465cb887d17a:203

I mistakenly invered the condition assuming it was a typo. I am now
removing it because it doesn't seem to be a problem anymore (plus it's a
dirty hack).

llvm-svn: 283639
2016-10-08 01:10:31 +00:00
Dylan McKay
6d9258b05a [AVR] Don't shadow container while iterating in range-based loop
This works on clang, but fails on GCC 4.6

llvm-svn: 283638
2016-10-08 01:09:06 +00:00
Dylan McKay
9bc70c9179 [AVR] Use references rather than pointers in AVRISelLowering
llvm-svn: 283636
2016-10-08 01:06:21 +00:00
Dylan McKay
bb08c7e2e9 Allow a maximum of 64 bits to be returned in registers
The rest spills to the stack

Authored by Jake Goulding

llvm-svn: 283635
2016-10-08 01:05:09 +00:00
Dylan McKay
1e3e36d597 [AVR] Expand MULHS for all types
Once MULHS was expanded, this exposed an issue where the condition
register was thought to be 16-bit. This caused an attempt to copy a
16-bit register to an 8-bit register.

Authored by Jake Goulding

llvm-svn: 283634
2016-10-08 01:01:49 +00:00
Dylan McKay
ba8fefd85c [AVR] Add the 'SoftFail' field to all instruction formats
This will be used in the future for disassembly.

llvm-svn: 283630
2016-10-08 00:55:46 +00:00
Dylan McKay
cec36d0272 [AVR] Set up the instruction printer and the assembly backend
llvm-svn: 283629
2016-10-08 00:50:11 +00:00
Dylan McKay
24c6381412 [AVR] Add dependencies to AVR libraries in AVRCodeGen
llvm-svn: 283628
2016-10-08 00:45:24 +00:00
Dylan McKay
4c9681ec4f [AVR] Add missing subdirectories to LLVMBuild
llvm-svn: 283627
2016-10-08 00:42:58 +00:00
Hal Finkel
e1cb0bd2ab [llvm-opt-report] Don't leave space for opts that never happen
Because screen space is precious, if an optimization (vectorization, for
example) never happens, don't leave empty space for the associated markers on
every line of the output. This makes the output much more compact, and allows
for the later inclusion of markers for more (although perhaps rare)
optimizations.

llvm-svn: 283626
2016-10-08 00:26:54 +00:00
Gor Nishanov
680815e118 [coroutines] Store an address of destroy OR cleanup part in the coroutine frame.
Summary:
If heap allocation of a coroutine is elided, we need to make sure that we will update an address stored in the coroutine frame from f.destroy to f.cleanup.
Before this change, CoroSplit synthesized these stores after coro.begin:

```
    store void (%f.Frame*)* @f.resume, void (%f.Frame*)** %resume.addr
    store void (%f.Frame*)* @f.destroy, void (%f.Frame*)** %destroy.addr

```

In those cases where we did heap elision, but were not able to devirtualize all indirect calls, destroy call will attempt to "free" the coroutine frame stored on the stack. Oops.

Now we use select to put an appropriate coroutine subfunction in the destroy slot. As bellow:

```
    store void (%f.Frame*)* @f.resume, void (%f.Frame*)** %resume.addr
    %0 = select i1 %need.alloc, void (%f.Frame*)* @f.destroy, void (%f.Frame*)* @f.cleanup
    store void (%f.Frame*)* %0, void (%f.Frame*)** %destroy.addr
```

Reviewers: majnemer

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D25377

llvm-svn: 283625
2016-10-08 00:22:50 +00:00
Lang Hames
230471705a [docs] Fix indentation bug in LangRef.
llvm-svn: 283624
2016-10-08 00:20:42 +00:00
Dylan McKay
2919eeaedd [AVR] Add the assembly printer
Summary: This adds the AVRAsmPrinter class.

Reviewers: arsenm, kparzysz

Subscribers: llvm-commits, wdng, beanz, japaric, mgorny

Differential Revision: https://reviews.llvm.org/D25271

llvm-svn: 283623
2016-10-08 00:02:36 +00:00
Tom Stellard
d2d7b48ba5 AMDGPU/SI: Handle div_fmas hazard in GCNHazardRecognizer
Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D25250

llvm-svn: 283622
2016-10-07 23:42:48 +00:00
Kyle Butt
71644ee1e5 Codegen: Tail-duplicate during placement.
The tail duplication pass uses an assumed layout when making duplication
decisions. This is fine, but passes up duplication opportunities that
may arise when blocks are outlined. Because we want the updated CFG to
affect subsequent placement decisions, this change must occur during
placement.

In order to achieve this goal, TailDuplicationPass is split into a
utility class, TailDuplicator, and the pass itself. The pass delegates
nearly everything to the TailDuplicator object, except for looping over
the blocks in a function. This allows the same code to be used for tail
duplication in both places.

This change, in concert with outlining optional branches, allows
triangle shaped code to perform much better, esepecially when the
taken/untaken branches are correlated, as it creates a second spine when
the tests are small enough.

Issue from previous rollback fixed, and a new test was added for that
case as well. Issue was worklist/scheduling/taildup issue in layout.

Issue from 2nd rollback fixed, with 2 additional tests. Issue was
tail merging/loop info/tail-duplication causing issue with loops that share
a header block.

Differential revision: https://reviews.llvm.org/D18226

llvm-svn: 283619
2016-10-07 22:33:20 +00:00
Arnold Schwaighofer
6fad756c74 swifterror: Don't compute swifterror vregs during instruction selection
The code used llvm basic block predecessors to decided where to insert phi
nodes. Instruction selection can and will liberally insert new machine basic
block predecessors. There is not a guaranteed one-to-one mapping from pred.
llvm basic blocks and machine basic blocks.

Therefore the current approach does not work as it assumes we can mark
predecessor machine basic block as needing a copy, and needs to know the set of
all predecessor machine basic blocks to decide when to insert phis.

Instead of computing the swifterror vregs as we select instructions, propagate
them at the end of instruction selection when the MBB CFG is complete.

When an instruction needs a swifterror vreg and we don't know the value yet,
generate a new vreg and remember this "upward exposed" use, and reconcile this
at the end of instruction selection.

This will only happen if the target supports promoting swifterror parameters to
registers and the swifterror attribute is used.

rdar://28300923

llvm-svn: 283617
2016-10-07 22:06:55 +00:00
Sanjay Patel
1d88c15c1d [DAG] clean up foldSelectOfConstants(); NFCI
Rename variables, simplify logic. 
Not clear yet why we don't handle a target with ZeroOrNegativeOneBooleanContent too.

llvm-svn: 283613
2016-10-07 21:55:42 +00:00
Davide Italiano
99e8d201a0 [InstCombine] Don't unpack arrays that are too large (part 2).
This is similar to r283599, but for store instructions.
Thanks to David for pointing out!

llvm-svn: 283612
2016-10-07 21:53:09 +00:00
Zachary Turner
fba0249962 Add missing include.
llvm-svn: 283610
2016-10-07 21:40:06 +00:00
Zachary Turner
4b8a9c1349 Refactor Symbol visitor code.
Type visitor code had already been refactored previously to
decouple the visitor and the visitor callback interface.  This
was necessary for having the flexibility to visit in different
ways (for example, dumping to yaml, reading from yaml, dumping
to ScopedPrinter, etc).

This patch merely implements the same visitation pattern for
symbol records that has already been implemented for type records.

llvm-svn: 283609
2016-10-07 21:34:46 +00:00
Hongbin Zheng
57e4e747e3 [cmake] Treat polly as "in tree" if LLVM_EXTERNAL_POLLY_SOURCE_DIR is provided
Differential Revision: https://reviews.llvm.org/D25354

llvm-svn: 283608
2016-10-07 21:32:47 +00:00
Davide Italiano
c6c98e0346 [InstCombine] Don't unpack arrays that are too large
Differential Revision:  https://reviews.llvm.org/D25376

llvm-svn: 283599
2016-10-07 20:57:42 +00:00
Sanjay Patel
b124036144 [DAG] move fold (select C, 0, 1 -> xor C, 1) to a helper function; NFC
We're missing at least 3 other similar folds based on what we have in InstCombine. 

llvm-svn: 283596
2016-10-07 20:47:51 +00:00
Tom Stellard
7128408133 AMDGPU/SI: Add support for 8-byte relocations
Reviewers: arsenm, kzhuravl

Subscribers: wdng, nhaehnle, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D25375

llvm-svn: 283593
2016-10-07 20:36:58 +00:00
Anna Thomas
99e41a98d7 [RS4GC] Strengthen coverage: add more tests
Summary: Add tests for cases where we have zero coverage in RS4GC.

Reviewers: sanjoy, reames

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25341

llvm-svn: 283591
2016-10-07 20:34:00 +00:00
Colin LeMahieu
c46eeafb38 [Hexagon][NFC] Using documented instruction type name V4LDST instead of MEMOP.
llvm-svn: 283582
2016-10-07 19:11:28 +00:00
Mehdi Amini
c7f513e186 Recommit "Use StringRef in LTOModule implementation (NFC)""
This reverts commit r283456 and reapply r282997, with explicitly
zeroing the struct member to workaround a bug in MSVC2013 with
zero-initialization: https://connect.microsoft.com/VisualStudio/feedback/details/802160

llvm-svn: 283581
2016-10-07 19:05:14 +00:00
Davide Italiano
f1729bd1f0 [LoopIdiomRecognize] Merge two if conditions into one. NFCI.
llvm-svn: 283579
2016-10-07 18:39:43 +00:00
Sanjay Patel
4b9d19b1ec [InstCombine] fold select X, (ext X), C
If we're going to canonicalize IR towards select of constants, try harder to create those.
Also, don't lose the metadata.

This is actually 4 related transforms in one patch:
      // select X, (sext X), C --> select X, -1, C
      // select X, (zext X), C --> select X,  1, C
      // select X, C, (sext X) --> select X, C, 0
      // select X, C, (zext X) --> select X, C, 0

Differential Revision: https://reviews.llvm.org/D25126

llvm-svn: 283575
2016-10-07 17:53:07 +00:00
Adam Nemet
1496f9df72 New utility to visualize optimization records
This is a new tool built on top of the new YAML ouput generated from
optimization remarks.  It produces HTML for easy navigation and
visualization.

The tool assumes that hotness information for the remarks is available
(the YAML file was produced with PGO).  It uses hotness to list the
remarks prioritized by the hotness on the index page.  Clicking the
source location of the remark in the list takes you the source where the
remarks are rendedered inline in the source.

For now, the tool is meant as prototype.

It's written in Python.  It uses PyYAML to parse the input.

Differential Revision: https://reviews.llvm.org/D25348

llvm-svn: 283571
2016-10-07 17:06:34 +00:00
Tom Stellard
0f9040e19e AMDGPU/SI: Emit fixups for long branches
Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D25366

llvm-svn: 283570
2016-10-07 16:01:18 +00:00
Simon Pilgrim
4fab02e083 [X86][SSE] Reapplied: Add vector fcopysign combine tests
Now with better lowering and fix for PR30443

llvm-svn: 283569
2016-10-07 16:00:59 +00:00
Artem Tamazov
d87d4169f2 [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.
Partially fixes Bug 28232.
Lit tests added.

Differential Revision: https://reviews.llvm.org/D25367

llvm-svn: 283567
2016-10-07 15:53:16 +00:00
Dehao Chen
00cca02991 Invoke add-discriminator at -g0 -fsample-profile
Summary: -fsample-profile needs discriminator, which will not be added if built with -g0. This patch makes sure the discriminator is added for sample-profile at -g0. A followup patch will be send out to update clang tests.

Reviewers: davidxl, dblaikie, echristo, dnovillo

Subscribers: mehdi_amini, probinson, llvm-commits

Differential Revision: https://reviews.llvm.org/D25132

llvm-svn: 283565
2016-10-07 15:21:31 +00:00
Matthew Simpson
c4d75790e7 [LV] Don't mark multi-use branch conditions uniform
Previously, we marked the branch conditions of latch blocks uniform after
vectorization if they were instructions contained in the loop. However, if a
condition instruction has users other than the branch, it may not remain
uniform. This patch ensures the conditions we mark uniform are only used by the
branch. This should fix PR30627.

Reference: https://llvm.org/bugs/show_bug.cgi?id=30627
llvm-svn: 283563
2016-10-07 15:20:13 +00:00
Krzysztof Parzyszek
daa0d1c208 Only track physical registers in LivePhysRegs
llvm-svn: 283561
2016-10-07 14:50:49 +00:00
Sam Kolton
cbf772ce03 [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h
Reviewers: artem.tamazov, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D25084

llvm-svn: 283560
2016-10-07 14:46:06 +00:00
Simon Pilgrim
24e66816ec [X86][SSE] Tidied up tests - use standard check prefixes
llvm-svn: 283559
2016-10-07 14:42:22 +00:00
Konstantin Zhuravlyov
12f780d0fd [AMDGPU] AMDGPUCodeGenPrepare: remove extra ';'
llvm-svn: 283558
2016-10-07 14:39:53 +00:00
Tom Stellard
6fa6d1d712 [ValueTracking] Fix crash in GetPointerBaseWithConstantOffset()
Summary:
While walking defs of pointer operands we were assuming that the pointer
size would remain constant.  This is not true, because addresspacecast
instructions may cast the pointer to an address space with a different
pointer width.

This partial reverts r282612, which was a more conservative solution
to this problem.

Reviewers: reames, sanjoy, apilipenko

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D24772

llvm-svn: 283557
2016-10-07 14:23:29 +00:00
Konstantin Zhuravlyov
602c1c7441 [AMDGPU] Promote uniform (i1, i16] operations to i32
Differential Revision: https://reviews.llvm.org/D25302

llvm-svn: 283555
2016-10-07 14:22:58 +00:00
Benjamin Kramer
257e127eaa Remove spurious non-printable character from source file.
NFC.

llvm-svn: 283552
2016-10-07 13:46:38 +00:00
Javed Absar
a39b9200fb [ARM]: add missing switch case for cortex-r52
Adds a missing switch case for handling cortex-r52
in init-subtarget-features.

llvm-svn: 283551
2016-10-07 13:41:55 +00:00