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105,525 Commits 4 Branches 5 Tags 704 MiB
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Commit Graph

261 Commits

Author SHA1 Message Date
Chris Lattner
8301d751ee Expose base opcode 
llvm-svn: 4742
 2002-11-18 06:56:24 +00:00
Chris Lattner
54bb9d64a3 Start to add more information to instr.def 
llvm-svn: 4741
 2002-11-18 05:37:11 +00:00
Chris Lattner
e921369cf7 Add instruction annotation about whether it has a 0x0F opcode prefix 
llvm-svn: 4740
 2002-11-18 01:59:28 +00:00
Chris Lattner
a7d7b16161 Arrange to have a TargetMachine available in X86InstrInfo::print 
llvm-svn: 4734
 2002-11-17 23:20:37 +00:00
Chris Lattner
5374a3be97 Reorganize printing interface a bit 
llvm-svn: 4728
 2002-11-17 22:53:13 +00:00
Chris Lattner
80f1f696e8 Add flag to specify when no value is produced by an instruction 
llvm-svn: 4441
 2002-10-30 01:09:34 +00:00
Chris Lattner
82479f668c Rename X86InstructionInfo to X86InstrInfo 
llvm-svn: 4413
 2002-10-29 21:05:24 +00:00
Chris Lattner
0518ad4aea Minor renaming 
llvm-svn: 4410
 2002-10-29 20:48:56 +00:00
Chris Lattner
9e3867d6d3 Implement MachineInstrInfo interface 
llvm-svn: 4394
 2002-10-29 17:43:19 +00:00
Chris Lattner
152b53fc64 Initial stab at MachineInstr'ication 
llvm-svn: 4367
 2002-10-28 23:55:19 +00:00
Chris Lattner
d25a097994 Initial checkin of X86 backend. 
We can instruction select exactly one instruction 'ret void'.  Wow.

llvm-svn: 4284
 2002-10-25 22:55:53 +00:00