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Commit Graph

272 Commits

Author SHA1 Message Date
Evan Cheng
f7637e403f A addressing mode folding enhancement:
Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
  return (x << 3) + 7;
}

This can be codegen'd as:
leal 7(,%eax,8), %eax

llvm-svn: 28550
2006-05-30 06:59:36 +00:00
Evan Cheng
550e73a900 Remove unused patterns.
llvm-svn: 28417
2006-05-20 01:40:16 +00:00
Evan Cheng
3a90665f14 - Use exact-width integer types, e.g. int32_t, to avoid confusion.
- Fix a couple of minor bugs in i16immSExt8 and i16immZExt8.
- Added loadiPTR fragment used for indirect jumps and calls.

llvm-svn: 28392
2006-05-19 18:40:54 +00:00
Evan Cheng
ff19d6478e Explicitly specify MOV32mi can only be used store 32-bit GV, etc.
llvm-svn: 28390
2006-05-19 07:30:36 +00:00
Evan Cheng
070813257a Use generic iPTR instead i32 to represent pointer type.
llvm-svn: 28371
2006-05-17 21:21:41 +00:00
Evan Cheng
dc9b5f5fc0 X86 integer register classes naming changes. Make them consistent with FP, vector classes.
llvm-svn: 28324
2006-05-16 07:21:53 +00:00
Evan Cheng
0fb3fc3626 Fixing truncate. Previously we were emitting truncate from r16 to r8 as
movw. That is we promote the destination operand to r16. So
        %CH = TRUNC_R16_R8 %BP
is emitted as
        movw %bp, %cx.

This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
        movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.

We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.

Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.

llvm-svn: 28164
2006-05-08 08:01:26 +00:00
Evan Cheng
0e9ec8d566 Need extload patterns after Chris' DAG combiner changes
llvm-svn: 28127
2006-05-05 08:23:07 +00:00
Evan Cheng
84612a59c2 Better implementation of truncate. ISel matches it to a pseudo instruction
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.

llvm-svn: 28119
2006-05-05 05:40:20 +00:00
Evan Cheng
11e3cec8bd Make x86 isel lowering produce tailcall nodes. They are match to normal calls
for now.

Patch contributed by Alexander Friedman.

llvm-svn: 27994
2006-04-27 08:40:39 +00:00
Nate Begeman
0d74cbcb6b Optimized stores to the constant pool, while cool, are unnecessary.
llvm-svn: 27948
2006-04-22 22:31:45 +00:00
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
2006-04-22 18:53:45 +00:00
Evan Cheng
169240beb7 - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377
2006-04-03 20:53:28 +00:00
Evan Cheng
875c895b0f Added missing (any_extend (load ...)) patterns.
llvm-svn: 27120
2006-03-25 09:45:48 +00:00
Chris Lattner
ec3f1b5cd1 Fix the encodings of these new instructions, hopefully fixing the JIT
failures from last night

llvm-svn: 26981
2006-03-23 16:13:50 +00:00
Nate Begeman
0ec15cd042 Add support for 8 bit immediates with 16/32 bit cmp instructions
llvm-svn: 26966
2006-03-23 01:29:48 +00:00
Evan Cheng
8dd794ea70 Use the generic vector register classes VR64 / VR128 rather than V4F32,
V8I16, etc.

llvm-svn: 26838
2006-03-18 01:23:20 +00:00
Evan Cheng
ee1a44d5d8 Move some pattern fragments to the right files.
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
Evan Cheng
d16fa97974 - Nuke 16-bit SBB instructions. We'll never use them.
- Nuke a bogus comment.

llvm-svn: 26815
2006-03-17 02:24:04 +00:00
Evan Cheng
d73d06f052 X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag.
llvm-svn: 26604
2006-03-07 23:34:23 +00:00
Evan Cheng
2327759419 Enable Dwarf debugging info.
llvm-svn: 26581
2006-03-07 02:02:57 +00:00
Chris Lattner
999aa36a04 remove the read/write port/io intrinsics.
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
Evan Cheng
995c9806ba * Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
* Add patterns to handle GlobalAddress, ConstantPool, etc.
  MOV32ri to materialize these nodes in registers.
  ADD32ri to handle %reg + GA, etc.
  MOV32mi to handle store GA, etc. to memory.

llvm-svn: 26374
2006-02-25 10:02:21 +00:00
Evan Cheng
cb9fb051a5 - Clean up the lowering and selection code of ConstantPool, GlobalAddress,
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.

llvm-svn: 26335
2006-02-23 20:41:18 +00:00
Evan Cheng
2977507828 PIC related bug fixes.
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.

llvm-svn: 26324
2006-02-23 02:43:52 +00:00
Evan Cheng
005de9e2bb Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
Fixed some existing bugs (wrong predicates, prefixes) at the same time.

llvm-svn: 26310
2006-02-22 02:26:30 +00:00
Evan Cheng
8ab6294f94 One more round of reorg so sabre doesn't freak out. :-)
llvm-svn: 26303
2006-02-21 20:00:20 +00:00
Evan Cheng
f7296d8fa5 A big more cleaning up.
llvm-svn: 26302
2006-02-21 19:30:30 +00:00
Evan Cheng
223d3a073a Moving things to their proper places.
llvm-svn: 26301
2006-02-21 19:26:52 +00:00
Evan Cheng
fee17dfff8 Split instruction info into multiple files, one for each of x87, MMX, and SSE.
llvm-svn: 26300
2006-02-21 19:13:53 +00:00
Evan Cheng
89553f1e86 Added separate alias instructions for SSE logical ops that operate on non-packed types.
llvm-svn: 26297
2006-02-21 02:24:38 +00:00
Evan Cheng
e68325d8aa Added MMX and XMM packed integer move instructions, movd and movq.
llvm-svn: 26296
2006-02-21 01:39:57 +00:00
Evan Cheng
6a9422ce1c Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294
2006-02-20 22:34:53 +00:00
Evan Cheng
b3d9ee74ad Added fisttp for fp to int conversion.
llvm-svn: 26283
2006-02-18 02:36:28 +00:00
Evan Cheng
bf3558a375 x86 / Darwin PIC support.
llvm-svn: 26273
2006-02-18 00:15:05 +00:00
Nate Begeman
9c0ab71f4a kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
2006-02-17 05:43:56 +00:00
Evan Cheng
9de0ad321a pxor (for FLD0SS) encoding was missing the OpSize prefix.
llvm-svn: 26244
2006-02-16 23:59:30 +00:00
Evan Cheng
bf4008c701 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241
2006-02-16 22:45:17 +00:00
Evan Cheng
af9730a217 MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
llvm-svn: 26234
2006-02-16 19:34:41 +00:00
Evan Cheng
da095e61c1 cvtsd2ss / cvtss2sd encoding bug.
llvm-svn: 26193
2006-02-15 00:31:03 +00:00
Evan Cheng
198d9447d6 movaps, movapd encoding bug.
llvm-svn: 26192
2006-02-15 00:11:37 +00:00
Chris Lattner
da4bd5c64e Eliminate the printCallOperand method, using a 'call' modifier on
printOperand instead.

llvm-svn: 26025
2006-02-06 23:41:19 +00:00
Evan Cheng
8fd9fd7866 Remove an unnecessary predicate.
llvm-svn: 25954
2006-02-04 02:23:01 +00:00
Evan Cheng
078962656b Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
flag so it can be flagged to a FST.

llvm-svn: 25953
2006-02-04 02:20:30 +00:00
Evan Cheng
b78bb375c2 Rearrange code to my liking. :)
llvm-svn: 25887
2006-02-01 23:01:57 +00:00
Evan Cheng
ef93bdc0cf - Use xor to clear integer registers (set R, 0).
- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.

llvm-svn: 25872
2006-02-01 06:13:50 +00:00
Evan Cheng
45ebd632f2 - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
- Use XORP* to implement fneg.

llvm-svn: 25857
2006-01-31 22:28:30 +00:00
Chris Lattner
5587b270e4 * Fix 80-column violations
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854
2006-01-31 19:43:35 +00:00
Evan Cheng
49467b6b5b Added custom lowering of fabs
llvm-svn: 25831
2006-01-31 03:14:29 +00:00
Evan Cheng
d2d96373dc Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
conversions. SSE does not have instructions to handle these tasks.

llvm-svn: 25817
2006-01-30 08:02:57 +00:00