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19820 Commits

Author SHA1 Message Date
Jim Grosbach
8987b277cb ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

llvm-svn: 144691
 2011-11-15 20:29:42 +00:00
Jim Grosbach
f0690cd90c ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

llvm-svn: 144689
 2011-11-15 20:14:51 +00:00
Jim Grosbach
8b1d4c989c ARM assembly parsing for two-operand form of 'mul' instruction. 
Ongoing rdar://10435114.

llvm-svn: 144688
 2011-11-15 20:02:06 +00:00
Jim Grosbach
6dbfffcbf7 Thumb2 two-operand 'mul' instruction wide encoding parsing. 
rdar://10449724

llvm-svn: 144684
 2011-11-15 19:55:16 +00:00
Owen Anderson
35f049f1fb Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
llvm-svn: 144683
 2011-11-15 19:55:00 +00:00
Jim Grosbach
df951fa128 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

llvm-svn: 144679
 2011-11-15 19:29:45 +00:00
Akira Hatanaka
040e92857f Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit 
registers and instructions when ABI is N64.

llvm-svn: 144666
 2011-11-15 18:53:55 +00:00
Akira Hatanaka
a6c12123f1 Set nomacro before emitting the sequence of instructions that set global pointer 
register.

llvm-svn: 144665
 2011-11-15 18:44:44 +00:00
Akira Hatanaka
666a872159 Simplify function PassByValArg64. 
llvm-svn: 144664
 2011-11-15 18:42:25 +00:00
Akira Hatanaka
4cbb3e4ca4 Delete files. 
llvm-svn: 144655
 2011-11-15 18:22:48 +00:00
Akira Hatanaka
ef7310d4a2 Remove MipsMCSymbolRefExpr. 
llvm-svn: 144654
 2011-11-15 18:20:08 +00:00
Jim Grosbach
61c3f1b35b ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions. 
rdar://10435076

llvm-svn: 144650
 2011-11-15 17:49:59 +00:00
Jay Foad
ebf2ec40e0 Fix typo in comment. 
llvm-svn: 144633
 2011-11-15 07:50:05 +00:00
Jay Foad
b4bb79247a Make use of MachinePointerInfo::getFixedStack. This removes all mention 
of PseudoSourceValue from lib/Target/.

llvm-svn: 144632
 2011-11-15 07:34:52 +00:00
Jay Foad
7d05fea7f8 Remove some unnecessary includes of PseudoSourceValue.h. 
llvm-svn: 144631
 2011-11-15 07:24:32 +00:00
Craig Topper
320d3ef477 Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled. 
llvm-svn: 144629
 2011-11-15 06:39:01 +00:00
Craig Topper
a584521daa Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370. 
llvm-svn: 144622
 2011-11-15 05:55:35 +00:00
Evan Cheng
47d8f8af84 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054

llvm-svn: 144608
 2011-11-15 02:12:34 +00:00
Jim Grosbach
2ac98a24aa ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

llvm-svn: 144606
 2011-11-15 01:46:57 +00:00
Jakob Stoklund Olesen
2709f65821 Break false dependencies before partial register updates. 
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

llvm-svn: 144602
 2011-11-15 01:15:30 +00:00
Jim Grosbach
6846540505 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

llvm-svn: 144593
 2011-11-14 23:43:46 +00:00
Jim Grosbach
a1a28df278 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

llvm-svn: 144592
 2011-11-14 23:32:59 +00:00
Jim Grosbach
8ec84fbe99 Add explanatory comment. 
llvm-svn: 144589
 2011-11-14 23:21:09 +00:00
Jim Grosbach
1d07736422 Split out the plain '.{8|16|32|64}' suffix handling. 
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.

llvm-svn: 144588
 2011-11-14 23:20:14 +00:00
Jim Grosbach
00283a5c8e ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

llvm-svn: 144587
 2011-11-14 23:11:19 +00:00
Chad Rosier
4e05d7f12c Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

llvm-svn: 144585
 2011-11-14 23:04:09 +00:00
Jim Grosbach
4a2f107b04 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
 2011-11-14 23:03:21 +00:00
Chad Rosier
48b92815e0 Add support for inlining small memcpys. 
rdar://10412592

llvm-svn: 144578
 2011-11-14 22:46:17 +00:00
Chad Rosier
8aa8f14940 Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.

llvm-svn: 144576
 2011-11-14 22:34:48 +00:00
Jim Grosbach
009733c9e4 ARM assembly parsing type suffix options for VLDR/VSTR. 
rdar://10435076

llvm-svn: 144575
 2011-11-14 22:28:39 +00:00
Evan Cheng
2034ff3b0b Add a missing pattern for X86ISD::MOVLPD. rdar://10436044 
llvm-svn: 144566
 2011-11-14 20:35:52 +00:00
Chad Rosier
65395ac4d0 Add support for Thumb load/stores with negative offsets. 
rdar://10412592

llvm-svn: 144565
 2011-11-14 20:22:27 +00:00
Benjamin Kramer
8450065be6 Unbreak Release builds. 
llvm-svn: 144560
 2011-11-14 19:51:48 +00:00
Pete Cooper
c9d6834f38 Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered 
Constant idx case is still done in tablegen but other cases are then expanded

Fixes <rdar://problem/10435460>

llvm-svn: 144557
 2011-11-14 19:38:42 +00:00
Akira Hatanaka
9dd2dd0320 32-to-64-bit extended load. 
llvm-svn: 144554
 2011-11-14 19:06:14 +00:00
Akira Hatanaka
282b708fcb AnalyzeCallOperands function for N32/64. 
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.

llvm-svn: 144553
 2011-11-14 19:02:54 +00:00
Akira Hatanaka
b147de0ada Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64. 
llvm-svn: 144552
 2011-11-14 19:01:09 +00:00
Justin Holewinski
4e7a1c571b PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations. 
llvm-svn: 144551
 2011-11-14 18:58:20 +00:00
Akira Hatanaka
db610fb423 Remove variable that keeps the size of area used to save byval or variable 
argument registers on the callee's stack frame, along with functions that set
and get it.
    
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.

llvm-svn: 144549
 2011-11-14 18:56:20 +00:00
Jim Grosbach
d791cf718c Tidy up. 80 column. 
llvm-svn: 144538
 2011-11-14 17:52:47 +00:00
Craig Topper
ee3a3cf35c Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions. 
llvm-svn: 144525
 2011-11-14 08:07:55 +00:00
Craig Topper
e0b34012db Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway. 
llvm-svn: 144522
 2011-11-14 06:46:21 +00:00
Chad Rosier
0e5094ca87 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592

llvm-svn: 144518
 2011-11-14 04:09:28 +00:00
Craig Topper
0c7b1d7cf1 Add BLSI, BLSMSK, and BLSR to getTargetNodeName. 
llvm-svn: 144502
 2011-11-13 17:31:07 +00:00
Chad Rosier
58ab241006 The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
llvm-svn: 144494
 2011-11-13 09:44:21 +00:00
Chad Rosier
8cfccc356e Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
llvm-svn: 144492
 2011-11-13 05:14:43 +00:00
Chad Rosier
0770c4834a Fix comments. 
llvm-svn: 144490
 2011-11-13 04:25:02 +00:00
Chad Rosier
acd199b5a4 Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

llvm-svn: 144488
 2011-11-13 02:23:59 +00:00
Craig Topper
0458cdf64a Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code. 
llvm-svn: 144457
 2011-11-12 09:58:49 +00:00
Akira Hatanaka
58e0babe25 Fix typo. 
llvm-svn: 144453
 2011-11-12 02:38:12 +00:00