Rafael Espindola
89ac048c5d
partial implementation of the ARM Addressing Mode 1
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llvm-svn: 30252
2006-09-11 17:25:40 +00:00
Rafael Espindola
20146be5e8
implement shl and sra
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llvm-svn: 30191
2006-09-08 17:36:23 +00:00
Rafael Espindola
9ffcdb8ab7
add the eor (xor) instruction
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llvm-svn: 30189
2006-09-08 16:59:47 +00:00
Rafael Espindola
af1689d5a5
implement unconditional branches
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fix select.ll
llvm-svn: 30186
2006-09-08 12:47:03 +00:00
Rafael Espindola
d9cebd5e48
add the orr instruction
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llvm-svn: 30125
2006-09-06 18:03:12 +00:00
Rafael Espindola
fb63eba81c
add the "eq" condition code
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implement a movcond instruction
llvm-svn: 29857
2006-08-24 17:19:08 +00:00
Rafael Espindola
cf999a6d39
create a generic bcond instruction that has a conditional code argument
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llvm-svn: 29856
2006-08-24 16:13:15 +00:00
Rafael Espindola
9e2a2dfb2d
initial support for branches
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llvm-svn: 29854
2006-08-24 13:45:55 +00:00
Rafael Espindola
474f6c5bf1
initial support for select
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llvm-svn: 29802
2006-08-21 22:00:32 +00:00
Rafael Espindola
13eb38e699
add the and instruction
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llvm-svn: 29793
2006-08-21 13:58:59 +00:00
Rafael Espindola
ff879761c1
add a "load effective address"
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llvm-svn: 29748
2006-08-17 17:09:40 +00:00
Rafael Espindola
b98e92cb78
Declare the callee saved regs
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Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
Evan Cheng
34a49551f5
CALLSEQ_* produces chain even if that's not needed.
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llvm-svn: 29603
2006-08-11 09:03:33 +00:00
Rafael Espindola
ae2d1c53c7
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
Rafael Espindola
fa94338687
add and use ARMISD::RET_FLAG
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llvm-svn: 29499
2006-08-03 17:02:20 +00:00
Rafael Espindola
719336441f
start comments with #
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move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save
llvm-svn: 29451
2006-08-01 18:53:10 +00:00
Rafael Espindola
9ea0bc742c
implemented sub
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correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
Rafael Espindola
ad256854c0
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
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llvm-svn: 29175
2006-07-18 17:00:30 +00:00
Rafael Espindola
40073f5767
skeleton of a lowerCall implementation for ARM
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llvm-svn: 29159
2006-07-16 01:02:57 +00:00
Rafael Espindola
fdfaee67f5
add the memri memory operand
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this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
Rafael Espindola
071c83dff0
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola
14a59f5b6e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
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fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
Rafael Espindola
1bf57da16e
Expand ret into "CopyToReg;BRIND"
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llvm-svn: 28559
2006-05-30 17:33:19 +00:00
Rafael Espindola
f7c5af4863
On ARM, alignment is in bits
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Add lr as a hard coded operand of bx
llvm-svn: 28494
2006-05-26 10:56:17 +00:00
Rafael Espindola
a0e82ff9be
implement movri
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add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
Rafael Espindola
dd49dfc0df
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00
