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Author SHA1 Message Date
Jim Grosbach
1cca1d4e60 ARM writeback vs. stride operands for VST/VLD. 
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.

llvm-svn: 143356
 2011-10-31 19:11:23 +00:00
Rafael Espindola
dd7a1f625b Move test to the X86 directory, note the PR number and only run MC once. 
llvm-svn: 143352
 2011-10-31 17:23:09 +00:00
Owen Anderson
d7700cb13f More not-crashing NEON disassembly updates for the vld refactoring. 
llvm-svn: 143351
 2011-10-31 17:17:32 +00:00
NAKAMURA Takumi
6b04733494 docs/*.html: Fix markups. 
llvm-svn: 143349
 2011-10-31 13:04:26 +00:00
NAKAMURA Takumi
c73cf858bb docs/*.html: Appease W3C Checker to add "charset=utf-8". 
llvm-svn: 143348
 2011-10-31 11:21:59 +00:00
Craig Topper
dbf10927d7 Fix operand type for int_x86_ssse3_phadd_sw_128 intrinsic 
llvm-svn: 143336
 2011-10-31 07:16:37 +00:00
Craig Topper
c0f93132bd Test case for X86 FS/GS Base intrinsics 
llvm-svn: 143332
 2011-10-31 02:15:47 +00:00
Craig Topper
6eaf58df7c Begin adding AVX2 instructions. No selection support yet other than intrinsics. 
llvm-svn: 143331
 2011-10-31 02:15:10 +00:00
Nick Lewycky
badcb1ff25 Close <div> that was indenting the rest of the page. 
llvm-svn: 143328
 2011-10-31 01:32:21 +00:00
Nick Lewycky
7308946be2 Switch new .file directive emission off by default, change llc's flag for it to 
-enable-dwarf-directory.

llvm-svn: 143326
 2011-10-31 01:06:02 +00:00
Craig Topper
f2a9bd3a4a Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. 
llvm-svn: 143319
 2011-10-30 19:57:21 +00:00
Duncan Sands
1077c1fa88 Reapply commit 143214 with a fix: m_ICmp doesn't match conditions 
with the given predicate, it matches any condition and returns the
predicate - d'oh!  Original commit message:
The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.

llvm-svn: 143318
 2011-10-30 19:56:36 +00:00
Craig Topper
daa1bc1e9a Mark X86 pcmpeq b/w/d intrinsics as being Commutative. pcmpeqq is already marked as Commutative. 
llvm-svn: 143317
 2011-10-30 18:33:35 +00:00
Peter Collingbourne
36e44c926d Teach ModuleLinker::getLinkageResult about materialisable functions 
llvm-svn: 143316
 2011-10-30 17:46:34 +00:00
Benjamin Kramer
c0001c42c6 X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in. 
llvm-svn: 143315
 2011-10-30 17:31:21 +00:00
Craig Topper
e77289b243 Fix return type for X86 mpsadbw instrinsic. The instruction takes in a vector of 8-bit integers, but produces a vector of 16-bit integers. 
llvm-svn: 143313
 2011-10-30 17:22:45 +00:00
Nadav Rotem
8282fc9e3b Fix pr11266. 
On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.

llvm-svn: 143311
 2011-10-30 13:24:22 +00:00
Benjamin Kramer
eb62811647 Silence compiler warning. 
llvm-svn: 143308
 2011-10-30 08:39:55 +00:00
Nadav Rotem
68400d352b Stabilize the test by specifying an exact cpu target 
llvm-svn: 143307
 2011-10-30 08:07:50 +00:00
Roman Divacky
c0f49b6277 Update on PPC32. 
llvm-svn: 143306
 2011-10-30 07:49:04 +00:00
Bill Wendling
c5c8918efc Do a relative path ln command instead of an absolute path one. Some people strangely enough have different directory layouts... 
llvm-svn: 143302
 2011-10-29 23:49:52 +00:00
NAKAMURA Takumi
ef79c816eb CREDITS.TXT: Add a line. (test commit) 
llvm-svn: 143300
 2011-10-29 23:42:14 +00:00
Nadav Rotem
6c79131e39 Add a new DAGCombine optimization for BUILD_VECTOR. 
If all of the inputs are zero/any_extended, create a new simple BV
which can be further optimized by other BV optimizations.

llvm-svn: 143297
 2011-10-29 21:23:04 +00:00
Benjamin Kramer
24c4266ada Force SSE for this test. 
llvm-svn: 143291
 2011-10-29 19:43:44 +00:00
Benjamin Kramer
7b1acc52c1 PPC: Disable moves for all CR subregisters. 
Should fix assertion failures on ppc buildbots.

llvm-svn: 143290
 2011-10-29 19:43:38 +00:00
Benjamin Kramer
d32c541fe4 SimplifyLibCalls: Use IRBuilder.CreateGlobalString when creating a string for printf->puts, which correctly sets the unnamed_addr bit on the resulting GlobalVariable. 
Fixes PR11264.

llvm-svn: 143289
 2011-10-29 19:43:31 +00:00
llvm
ce47648159 Test. 
llvm-svn: 143277
 2011-10-29 14:16:39 +00:00
Bill Wendling
61e2b39b06 Revise ThreadSanitizer mention so that it lists the correct frontends. 
llvm-svn: 143268
 2011-10-29 01:11:15 +00:00
Bill Wendling
f102657a93 Add Cling to the External Projects list. 
llvm-svn: 143267
 2011-10-29 01:10:01 +00:00
Eli Friedman
7c9bef9ba8 Revert r143214; it's breaking a bunch of stuff. 
llvm-svn: 143265
 2011-10-29 00:56:07 +00:00
Dan Gohman
826cec9a4b Revert r143206, as there are still some failing tests. 
llvm-svn: 143262
 2011-10-29 00:41:52 +00:00
NAKAMURA Takumi
78a0f170d6 test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now. 
llvm-svn: 143247
 2011-10-28 23:11:03 +00:00
Jim Grosbach
37119b8a01 ARM mode 'mov' to 'mvn' assembler alias. 
llvm-svn: 143237
 2011-10-28 22:50:54 +00:00
Jim Grosbach
f3285dba99 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

llvm-svn: 143235
 2011-10-28 22:36:30 +00:00
Jim Grosbach
3d628952f6 Allow InstAlias's to use immediate matcher patterns that xform the value. 
For example,

On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.

llvm-svn: 143233
 2011-10-28 22:32:53 +00:00
Owen Anderson
9e033c5b03 Fix illegal disassembly testcase. 
llvm-svn: 143231
 2011-10-28 21:45:09 +00:00
Jim Grosbach
7a4e1e2e0b Clarify example snippets a bit. 
llvm-svn: 143224
 2011-10-28 20:52:20 +00:00
Owen Anderson
5fdb303642 Specify that the high bit of the alignment field is fixed to 0 on these instructions. 
llvm-svn: 143220
 2011-10-28 20:43:24 +00:00
Akira Hatanaka
f71673c585 Make changes necessary in LowerFormalArguments to support Mips64. 
llvm-svn: 143218
 2011-10-28 19:55:48 +00:00
Akira Hatanaka
3069ec27da Make changes necessary in LowerCall to support Mips64. 
llvm-svn: 143217
 2011-10-28 19:49:00 +00:00
Duncan Sands
7791a854c3 The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false. 
Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.

llvm-svn: 143214
 2011-10-28 19:01:20 +00:00
Akira Hatanaka
856f4e30b2 Add variable IsO32 to MipsTargetLowering. 
llvm-svn: 143213
 2011-10-28 18:47:24 +00:00
Duncan Sands
3483c23658 A shift of a power of two is a power of two or zero. 
For completeness - not spotted in the wild.

llvm-svn: 143211
 2011-10-28 18:30:05 +00:00
Duncan Sands
5730fe6a31 Fold icmp ugt (udiv X, Y), X to false. Spotted by my super-optimizer 
in 186.crafty.

llvm-svn: 143209
 2011-10-28 18:17:44 +00:00
Owen Anderson
3dd6c949a5 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
llvm-svn: 143208
 2011-10-28 18:02:13 +00:00
Dan Gohman
dedcc22bcd Reapply r143177 and r143179 (reverting r143188), with scheduler 
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.

llvm-svn: 143206
 2011-10-28 17:55:38 +00:00
Owen Anderson
5ccc0979a0 Revert r143202. 
llvm-svn: 143203
 2011-10-28 17:38:30 +00:00
Owen Anderson
5c58be2852 Specify fixed bits on CPS instructions to enable roundtripping. 
llvm-svn: 143202
 2011-10-28 17:29:39 +00:00
Jim Grosbach
72ab459378 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
 2011-10-28 16:57:07 +00:00
Jim Grosbach
188121af2e Allow register classes to match a containing class in InstAliases. 
If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.

llvm-svn: 143200
 2011-10-28 16:43:40 +00:00