1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Commit Graph

211611 Commits

Author SHA1 Message Date
Wang, Pengfei
2da858213e [X86] Fix a codegen crash in getSetCCResultType
This patch fixes some crashes coming from
X86ISelLowering::getSetCCResultType, which would occasionally return
an EVT constructed from an invalid MVT, which has a null Type pointer.

This patch refers to D95434.

Differential Revision: https://reviews.llvm.org/D97036
2021-02-19 17:30:10 +08:00
Sjoerd Meijer
23fb2ffcc6 [AArch64] Add some missing Neoverse features
This enables AES fusion and the post RA scheduler for the Neoverse cores.
And while we are it also for the A55 that we had missed earlier.

Differential Revision: https://reviews.llvm.org/D96866
2021-02-19 09:18:35 +00:00
Qiu Chaofan
41dafb0875 [llvm-exegesis] Ignore instructions using custom inserter
Some instructions defined in table-gen files sets usesCustomInserter
bit, which means it has to be lowered by target code and isn't actually
valid instruction at MC level. So we should treat them like pseudo
instructions.

Reviewed By: gchatelet

Differential Revision: https://reviews.llvm.org/D94898
2021-02-19 17:04:27 +08:00
Qiu Chaofan
48961acee2 [llvm-exegesis] [PowerPC] Add basic LIT test
Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D94897
2021-02-19 17:01:05 +08:00
David Green
20be3bc420 [NPM][LTO] Do not enable MemorySSA with LoopFullUnrollPass
As with the standard opt pipeline, we disable the MemorySSA dependency
in the LTO LPM pipeline as not all passes preserve MemorySSA.
2021-02-19 08:35:11 +00:00
Djordje Todorovic
38dcbfd498 Reland "[Debugify] Make the debugify aware of the original (-g) Debug Info"
As discussed on the RFC [0], I am sharing the set of patches that
    enables checking of original Debug Info metadata preservation in
    optimizations. The proof-of-concept/proposal can be found at [1].

    The implementation from the [1] was full of duplicated code,
    so this set of patches tries to merge this approach into the existing
    debugify utility.

    For example, the utility pass in the original-debuginfo-check
    mode could be invoked as follows:

      $ opt -verify-debuginfo-preserve -pass-to-test sample.ll

    Since this is very initial stage of the implementation,
    there is a space for improvements such as:
      - Add support for the new pass manager
      - Add support for metadata other than DILocations and DISubprograms

    [0] https://groups.google.com/forum/#!msg/llvm-dev/QOyF-38YPlE/G213uiuwCAAJ
    [1] https://github.com/djolertrk/llvm-di-checker

    Differential Revision: https://reviews.llvm.org/D82545

The test that was failing is now forced to use the old PM.
2021-02-18 23:29:22 -08:00
Craig Topper
276f5e9168 [RISCV] Prune unneeded indexed load/store pseudo instructions.
We were creating more combinations of value and index lmul than
we needed.

I've copied the loop structure used here from VPseudoAMOEI with
all data sew values instead of just 32/64.

Similar can be done for segment loads/store.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D97008
2021-02-18 23:08:39 -08:00
Kazu Hirata
249aa54f98 [CodeGen] Use range-based for loops (NFC) 2021-02-18 22:46:43 -08:00
Kazu Hirata
3912ea99c3 [Support] Use static_assert instead of assert (NFC)
Identified with misc-static-assert.
2021-02-18 22:46:41 -08:00
Kazu Hirata
6e1c09263f [TableGen] Use ListSeparator (NFC) 2021-02-18 22:46:39 -08:00
Serge Pavlov
dece4f91fe [FPEnv][AArch64] Implement lowering of llvm.set.rounding
Differential Revision: https://reviews.llvm.org/D96836
2021-02-19 13:16:51 +07:00
Lang Hames
04856db5a7 [ORC] Print CPU feature string in JITTargetMachineBuilder debugging output. 2021-02-19 15:18:19 +11:00
Hsiangkai Wang
f6e848a7ad [RISCV] Remove redundant test cases for index segment store (8/8).
Differential Revision: https://reviews.llvm.org/D97026
2021-02-19 11:56:08 +08:00
Hsiangkai Wang
357e4f3917 [RISCV] Remove redundant test cases for index segment store (7/8).
Differential Revision: https://reviews.llvm.org/D97025
2021-02-19 11:56:08 +08:00
Hsiangkai Wang
4add710dfe [RISCV] Remove redundant test cases for index segment store (6/8).
Differential Revision: https://reviews.llvm.org/D97024
2021-02-19 11:56:08 +08:00
Hsiangkai Wang
f7ff20372e [RISCV] Remove redundant test cases for index segment store (5/8).
Differential Revision: https://reviews.llvm.org/D97023
2021-02-19 11:56:08 +08:00
Hsiangkai Wang
ac06866964 [RISCV] Remove redundant test cases for index segment load (4/8). 2021-02-19 11:56:08 +08:00
Hsiangkai Wang
cda993b111 [RISCV] Remove redundant test cases for index segment load (3/8).
Differential Revision: https://reviews.llvm.org/D97022
2021-02-19 11:56:08 +08:00
Hsiangkai Wang
750c265389 [RISCV] Remove redundant test cases for index segment load (2/8). 2021-02-19 11:56:08 +08:00
Hsiangkai Wang
34129d71d5 [RISCV] Remove redundant test cases for index segment load (1/8).
Differential Revision: https://reviews.llvm.org/D97020
2021-02-19 11:56:08 +08:00
Xun Li
f44a013c0b [Coroutine] Relax CoroElide musttail check
As discussed in D94834, we don't really need to do complicated analysis. It's safe to just drop the tail call attribute.

Differential Revision: https://reviews.llvm.org/D96926
2021-02-18 19:36:11 -08:00
Craig Topper
5ba4ec05cc [RISCV] Split zvlsseg searchable table into 4 separate tables. Index by properties rather than intrinsic ID.
Intrinsic ID is a 32-bit value which made each row of the table 4
byte aligned. The remaining fields used 5 bytes. This meant 3 bytes
of padding per row.

This patch breaks the table into 4 separate tables and indexes them
by properties we know about the intrinsic. NF, masked,
strided, ordered, etc. The indexed load/store tables have no
padding in their rows now.

All together this reduces the size of llc binary by ~28K.

I'm considering adding similar tables for isel of non-segment
load/store as well to cut down the size of the isel table and
probably improve our isel performance. Those tables would need to
indexed from intrinsics, IR loads/stores, gathers/scatters, and
RISCVISD opcodes. So having a table that can be indexed without using
intrinsic ID is more flexible.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D96894
2021-02-18 19:00:49 -08:00
Craig Topper
be46ec7d63 [RISCV] Enable PrimaryKeyEarlyOut on RISCVVPseudosTable.
This table is queried in RISCVMCInstLower without knowing
whether the instruction is a vector pseudo. Due to the way the
binary search works, we have to do log2(tablesize) checks just
to determine a non-vector instruction isn't in the table.

Conveniently, all the vector pseudos are pretty tightly
packed within the internal instruction enum. By enabling the
PrimaryKeyEarlyOut, tablegen will emit a check against the
beginning and end of the table before doing the binary search.
This gives a quick early out on the search for the majority
of non-vector instructions.

Differential Revision: https://reviews.llvm.org/D97016
2021-02-18 18:59:32 -08:00
Adrian Prantl
5446af1778 Reset the EntryValue location flag in finalizeEntryValue.
This fixes an assertion error when entry values are combined with
DW_OP_LLVM_fragment.
2021-02-18 18:36:36 -08:00
Konstantin Zhuravlyov
7646090a8e AMDGPU/ELF: Sort MACHs by value and add missing reserved MACHs
- Sort MACHs by its value
  - Add missing reserved MACHs
    - EF_AMDGPU_MACH_AMDGCN_RESERVED_0X3D
    - EF_AMDGPU_MACH_AMDGCN_RESERVED_0X3E

Differential Revision: https://reviews.llvm.org/D97010
2021-02-18 20:46:27 -05:00
Wei Mi
1344e2b49c [SampleFDO] Stop repeated indirect call promotion for the same target.
Found a problem in indirect call promotion in sample loader pass. Currently
if an indirect call is promoted for a target, and if the parent function is
inlined into some other function, the indirect call can be promoted for the
same target again. That is redundent which can harm performance and can cause
excessive compile time in some extreme case.

The patch fixes the issue. If a target is promoted for an indirect call, the
patch will write ICP metadata with the target call count being set to 0.
In the later ICP in sample profile loader, if it sees a target has 0 count
for an indirect call, it knows the target has been promoted and won't do
indirect call promotion for the indirect call.

The fix brings 0.1~0.2% performance on our search benchmark.

Differential Revision: https://reviews.llvm.org/D96806
2021-02-18 17:01:32 -08:00
Matt Arsenault
b9ed6d64dc MIR: Fix parser crash on syntax error on first character
This was calling the diagnostic printer before the context member was
initialized.
2021-02-18 18:59:08 -05:00
Jianzhou Zhao
fc057bebb5 [dfsan] Instrument origin variable and function definitions
This is a part of https://reviews.llvm.org/D95835.

Reviewed-by: morehouse, gbalats

Differential Revision: https://reviews.llvm.org/D96977
2021-02-18 23:50:05 +00:00
Leonard Chan
b854304d0e [llvm][IR] Do not place constants with static relocations in a mergeable section
This patch provides two major changes:

1. Add getRelocationInfo to check if a constant will have static, dynamic, or
   no relocations. (Also rename the original needsRelocation to needsDynamicRelocation.)
2. Only allow a constant with no relocations (static or dynamic) to be placed
   in a mergeable section.

This will allow unused symbols that contain static relocations and happen to
fit in mergeable constant sections (.rodata.cstN) to instead be placed in
unique-named sections if -fdata-sections is used and subsequently garbage collected
by --gc-sections.

See https://lists.llvm.org/pipermail/llvm-dev/2021-February/148281.html.

Differential Revision: https://reviews.llvm.org/D95960
2021-02-18 15:39:00 -08:00
Nico Weber
89f39afb65 [gn build] assert that goma_dir and sysroot are set for goma builds 2021-02-18 18:30:26 -05:00
Hongtao Yu
9372bfe8ed [CSSPGO] Use callsite sample counts to annotate indirect call sites.
With CSSPGO all indirect call targets are counted torwards the original indirect call site in the profile, including both inlined and non-inlined targets. Therefore no need to look for callee entry counts. This also fixes the issue where callee entry count doesn't match callsite count due to the nature of CS sampling.

I'm also cleaning up the orginal code that called `findIndirectCallFunctionSamples` just to compute the sum, the return value of which was disgarded.

Reviewed By: wmi, wenlei

Differential Revision: https://reviews.llvm.org/D96990
2021-02-18 14:52:34 -08:00
Matt Arsenault
c8d672e931 AMDGPU: Add regression testcase for bundle pressure issue
This is a somewhat reduced testcase that regressed, causing the revert
in 477e3fe4f874b1c4d5896f3bfaf7b3b8a6d38103.

This was producing a bundle that could not be allocated. This is a
tricky one to reduce/reproduce, but I do like having some sanity check
for this.
2021-02-18 17:39:33 -05:00
Petr Hosek
d548975423 [Coverage] Store compilation dir separately in coverage mapping
We currently always store absolute filenames in coverage mapping.  This
is problematic for several reasons. It poses a problem for distributed
compilation as source location might vary across machines.  We are also
duplicating the path prefix potentially wasting space.

This change modifies how we store filenames in coverage mapping. Rather
than absolute paths, it stores the compilation directory and file paths
as given to the compiler, either relative or absolute. Later when
reading the coverage mapping information, we recombine relative paths
with the working directory. This approach is similar to handling
ofDW_AT_comp_dir in DWARF.

Finally, we also provide a new option, -fprofile-compilation-dir akin
to -fdebug-compilation-dir which can be used to manually override the
compilation directory which is useful in distributed compilation cases.

Differential Revision: https://reviews.llvm.org/D95753
2021-02-18 14:34:39 -08:00
Matt Arsenault
2dc47494f2 GlobalISel: Merge some AMDGPU ABI lowering code to generic code
AMDGPU currently has a lot of pre-processing code to pre-split
argument types into 32-bit pieces before passing it to the generic
code in handleAssignments. This is a bit sloppy and also requires some
overly fancy iterator work when building the calls. It's better if all
argument marshalling code is handled directly in
handleAssignments. This handles more situations like decomposing large
element vectors into sub-element sized pieces.

This should mostly be NFC, but does change the generated code by
shifting where the initial argument packing instructions are placed. I
think this is nicer looking, since it now emits the packing code
directly after the relevant copies, rather than after the copies for
the remaining arguments.

This doubles down on gfx6/gfx7 using the gfx8+ ABI for 16-bit
types. This is ultimately the better option, but incompatible with the
DAG. Fixing this requires more work, especially for f16.
2021-02-18 17:26:55 -05:00
Nikita Popov
9fa93a3e70 [BasicAA] Always strip single-argument phi nodes
We can always look through single-argument (LCSSA) phi nodes when
performing alias analysis. getUnderlyingObject() already does this,
but stripPointerCastsAndInvariantGroups() does not. We still look
through these phi nodes with the usual aliasPhi() logic, but
sometimes get sub-optimal results due to the restrictions on value
equivalence when looking through arbitrary phi nodes. I think it's
generally beneficial to keep the underlying object logic and the
pointer cast stripping logic in sync, insofar as it is possible.

With this patch we get marginally better results:

  aa.NumMayAlias | 5010069 | 5009861
  aa.NumMustAlias | 347518 | 347674
  aa.NumNoAlias | 27201336 | 27201528
  ...
  licm.NumPromoted | 1293 | 1296

I've renamed the relevant strip method to stripPointerCastsForAliasAnalysis(),
as we're past the point where we can explicitly spell out everything
that's getting stripped.

Differential Revision: https://reviews.llvm.org/D96668
2021-02-18 23:07:50 +01:00
Simon Pilgrim
488d2af727 [DAG] getTruncatedUSUBSAT - always truncate operands. NFCI.
As noticed on D96703, we're always truncating the operands so should use getNode(ISD::TRUNCATE) instead of getZExtOrTrunc.
2021-02-18 21:28:55 +00:00
Guozhi Wei
4131403905 [DAGCombiner] Transform (zext (select c, load1, load2)) -> (select c, zextload1, zextload2)
If extload is legal, following transform
    (zext (select c, load1, load2)) -> (select c, zextload1, zextload2)
can save one ext instruction.

Differential Revision: https://reviews.llvm.org/D95086
2021-02-18 13:15:20 -08:00
Nico Weber
1f0fc8fadb [gn build] kind of merge f020544601
Fixes check-llvm with a clean build dir.
2021-02-18 16:12:32 -05:00
Nikita Popov
721457029a [DCE] Add tests for non-willreturn function being removed (NFC) 2021-02-18 21:56:20 +01:00
Petr Hosek
8ce86e4200 Revert "[Coverage] Store compilation dir separately in coverage mapping"
This reverts commit 97ec8fa5bb07e3f5bf25ddcb216b545cd3d03b65 since
the test is failing on some bots.
2021-02-18 12:50:24 -08:00
Ta-Wei Tu
4ec18a580a Remove redundent types in pr49185.ll 2021-02-19 04:44:27 +08:00
Craig Topper
604f57507d [RISCV] Simplify VPseudoAMOEI multiclass. NFC
lmul was already iterated in one of the loops. We don't need to recreate
it from a string.
2021-02-18 12:40:51 -08:00
Stanislav Mekhanoshin
ce925aa3d2 [AMDGPU] Correct gfx90c feature list
Looks like we have forced FeatureXNACK and forgot
FeatureMadMacF32Insts.

Differential Revision: https://reviews.llvm.org/D96989
2021-02-18 12:40:27 -08:00
Petr Hosek
fd85f23c36 [Coverage] Store compilation dir separately in coverage mapping
We currently always store absolute filenames in coverage mapping.  This
is problematic for several reasons. It poses a problem for distributed
compilation as source location might vary across machines.  We are also
duplicating the path prefix potentially wasting space.

This change modifies how we store filenames in coverage mapping. Rather
than absolute paths, it stores the compilation directory and file paths
as given to the compiler, either relative or absolute. Later when
reading the coverage mapping information, we recombine relative paths
with the working directory. This approach is similar to handling
ofDW_AT_comp_dir in DWARF.

Finally, we also provide a new option, -fprofile-compilation-dir akin
to -fdebug-compilation-dir which can be used to manually override the
compilation directory which is useful in distributed compilation cases.

Differential Revision: https://reviews.llvm.org/D95753
2021-02-18 12:27:42 -08:00
Sam Powell
3bda5a764e [llvm][TextAPI] add equality operator for InterfaceFile
This patch adds functionality to compare for the equality between `InterfaceFile`s based on attributes specific to linking.

Reviewed By: cishida, steven_wu

Differential Revision: https://reviews.llvm.org/D96629
2021-02-18 11:53:08 -08:00
Wouter van Oortmerssen
c0b486e8f3 [WebAssembly] Fix assert in lookup of section symbols
Fixes assert in: https://bugs.llvm.org/show_bug.cgi?id=49036

getWasmSection creates sections if they don't exist, but doesn't add them to the Symbols table. This may cause problems in subsequent calls to getOrCreateSymbol which checks this table, the calls createSymbol assuming it doesn't exist, which then checks UsedNames and finds out it does exist, causing an assert on trying to rename a non-temp symbol.

I tried also fixing the somewhat unintuitive forced suffixing (adding `0`), but it turns out that WasmObjectWriter currently assumes these section symbols are unique, so that may have to be a separate fix: https://bugs.llvm.org/show_bug.cgi?id=49252

Also worth noting is that getWasmSection calling createSymbol may not be correct to start with, given that createSymbol seems to assume it is creating non-section symbols. But again, for a future fix.

Related: where some of this was introduced: 8d396acac3

Differential Revision: https://reviews.llvm.org/D96473
2021-02-18 11:50:14 -08:00
Craig Topper
4fb5ffafaa [RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests.
The expansions of the saturating intrinsics can make use of
the min(u)/max(u) instructions in Zbb.
2021-02-18 11:41:45 -08:00
Nico Weber
5d1a8a5c59 [gn build] try to fix libxml2 include path on mac after 0ec448194e29 2021-02-18 14:40:14 -05:00
Jessica Clarke
55ebf0201e [RISCV] Use XLenRI alias for RegInfoByHwMode instances
This avoids tedious repetition and matches what we do for the
ValueTypeByHwMode uses.

Reviewed By: craig.topper, luismarques

Differential Revision: https://reviews.llvm.org/D96649
2021-02-18 19:38:36 +00:00
Guozhi Wei
b64a3665e6 Pre-commit test case
Pre-commit test case for https://reviews.llvm.org/D95086, so that patch
can show the actual diff.
2021-02-18 11:05:29 -08:00