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Commit Graph

164386 Commits

Author SHA1 Message Date
Peter Collingbourne
2882a797e8 ARM: Remove unnecessary argument. NFCI.
IsLittleEndian is already a field of ARMAsmBackend.

llvm-svn: 332420
2018-05-16 00:21:47 +00:00
Peter Collingbourne
1de7d6ca5c ARM: Deduplicate code and remove unnecessary declaration. NFCI.
llvm-svn: 332419
2018-05-16 00:21:31 +00:00
Anastasis Grammenos
659d2bd0dd [Debugify] Fix test failing after r332416
I missed a test that needed an update.

Failing bot: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/30071

llvm-svn: 332418
2018-05-16 00:11:52 +00:00
Anastasis Grammenos
1d797ae8dd [Debugfiy] Print the pass name next to the result
CheckDebugify now prints the pass name right next to the result of the check.

Differential Revision: https://reviews.llvm.org/D46908

llvm-svn: 332416
2018-05-15 23:38:05 +00:00
Eli Friedman
6893497aee [MachineOutliner] Add optsize markings to outlined functions.
It doesn't matter much this late in the pipeline, but one place that
does check for it is the function alignment code.

Differential Revision: https://reviews.llvm.org/D46373

llvm-svn: 332415
2018-05-15 23:36:46 +00:00
Simon Pilgrim
fc8050932b [X86][SSE] Add tests for vector rotates by splat variable.
llvm-svn: 332410
2018-05-15 22:11:51 +00:00
Stanislav Mekhanoshin
f59c5c4f0d [AMDGPU] Fix handling of void types in isLegalAddressingMode
It is legal for the type passed to isLegalAddressingMode to be
unsized or, more specifically, VoidTy. In this case, we must
check the legality of load / stores for all legal types. Directly
trying to call getTypeStoreSize is incorrect, and leads to breakage
in e.g. Loop Strength Reduction. This change guards against that
behaviour.

Differential Revision: https://reviews.llvm.org/D40405

llvm-svn: 332409
2018-05-15 22:07:51 +00:00
Sanjay Patel
f00312f0b4 [InstCombine] fix binop (shuffle X), C --> shuffle (binop X, C') to check uses
llvm-svn: 332407
2018-05-15 22:00:37 +00:00
Sam Clegg
c52f903824 [WebAssembly] Provide WasmFunction content offset information.
WasmObjectWriter mostly operates with function segments offsets that do
not include their size fields. WasmObjectFile needs to have and provide
this information to the lld to maintain proper
R_WEBASSEMBLY_FUNCTION_OFFSET_I32 relocations entries.

Patch by Yury Delendik

Differential Revision: https://reviews.llvm.org/D46763

llvm-svn: 332406
2018-05-15 21:49:58 +00:00
Marek Olsak
738dbad110 AMDGPU: Add a missing test for the 128-bit local addr space option
This should have been pushed with:
  "AMDGPU: enable 128-bit for local addr space under an option"

llvm-svn: 332404
2018-05-15 21:41:57 +00:00
Marek Olsak
99f1ffda4e StructurizeCFG: fix inverting conditions
Author: Samuel Pitoiset

Without this patch, it appears to me that we are selecting
the wrong operand when inverting conditions. In the attached
test, it will select %tmp3 instead of %tmp4. To fix it, just
use 'A' as everywhere.

This fixes a regression introduced by
"[PatternMatch] define m_Not using m_Xor and cst_pred_ty"

https://reviews.llvm.org/D46351

llvm-svn: 332403
2018-05-15 21:41:55 +00:00
Evgeniy Stepanov
af03237a89 [msan] Instrument masked.store, masked.load intrinsics.
Summary: Instrument masked store/load intrinsics.

Reviewers: kcc

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D46785

llvm-svn: 332402
2018-05-15 21:28:25 +00:00
Benjamin Kramer
cc1be5b711 Move helper classes into anonymous namespaces. NFCI.
llvm-svn: 332400
2018-05-15 21:26:47 +00:00
Sanjay Patel
7a08ae357f [InstCombine] clean up code for binop-shuffle transforms; NFCI
llvm-svn: 332399
2018-05-15 21:23:58 +00:00
Jake Ehrlich
b63074777b [llvm-objcopy] Add --only-keep-debug as a noop
This option just keeps being a problem and really needs to be implemented
in some fashion. Implementing it properly requires some kind of
"replaceSectionReference" method because all the existing links need to be
maintained. The desired behavior is just for allocated sections to become
NOBITS but actually implementing that is rather tricky due to the current
design of llvm-objcopy. However converting allocated sections to NOBITS is
just an optimization and not something debuggers need. Debuggers can debug
a stripped executable and take an unstripped executable for that stripped
executable as input. Additionally allocated sections account for a very
small part of debug binaries so this optimization is quite small. I propose
that for the time being we implement this as a NOP so that people can use
llvm-objcopy where they need to, just in a sub-optimal way.

This option has already blocked a lot of people and its currently blocking me.

llvm-svn: 332396
2018-05-15 20:53:53 +00:00
Evandro Menezes
32ec7fd07b [AArch64] Improve single vector lane unscaled stores
When storing the 0th lane of a vector, use a simpler and usually more
efficient scalar store instead.  In this case, also using the unscaled
offset.

Differential revision: https://reviews.llvm.org/D46762

llvm-svn: 332394
2018-05-15 20:41:12 +00:00
Sanjay Patel
7e550a827a [InstCombine] add more tests for binop-shuffle; NFC
The splat pattern is part of PR37463:
https://bugs.llvm.org/show_bug.cgi?id=37463

llvm-svn: 332393
2018-05-15 20:34:09 +00:00
Nirav Dave
803a183ac3 [DAGCombine] Move load checks on store of loads into candidate
search. NFCI.

Migrate single-use and non-volatility, non-indexed requirements on
stores of immediate store values to candidate collection pass from
later stage.

llvm-svn: 332392
2018-05-15 20:31:53 +00:00
Peter Collingbourne
1d0cf91132 Nios2: Unbreak build.
llvm-svn: 332391
2018-05-15 20:21:58 +00:00
Matt Davis
efffaf5cb4 [llvm-mca] Introduce a pipeline Stage class and FetchStage.
Summary:
    This is just an idea, really two ideas.  I expect some push-back,
    but I realize that posting a diff is the most comprehensive way to express
    these concepts.

    This patch introduces a Stage class which represents the
    various stages of an instruction pipeline.  As a start, I have created a simple
    FetchStage that is based on existing logic for how MCA produces
    instructions, but now encapsulated in a Stage.  The idea should become more concrete
    once we introduce additional stages.  The idea being, that when a stage completes,
    the next stage in the pipeline will be executed.  Stages are chained together
    as a singly linked list to closely model a real pipeline. For now there is only one stage,
    so the stage-to-stage flow of instructions isn't immediately obvious.

    Eventually, Stage will also handle event notifications, but that functionality
    is not complete, and not destined for this patch.  Ideally, an interested party 
    can register for notifications from a particular stage.  Callbacks will be issued to
    these listeners at various points in the execution of the stage.  
    For now, eventing functionality remains similar to what it has been in mca::Backend. 
    We will be building-up the Stage class as we move on, such as adding debug output.

    This patch also removes the unique_ptr<Instruction> return value from
    InstrBuilder::createInstruction.  An Instruction pointer is still produced,
    but now it's up to the caller to decide how that item should be managed post-allocation
    (e.g., smart pointer).  This allows the Fetch stage to create instructions and
    manage the lifetime of those instructions as it wishes, and not have to be bound to any
    specific managed pointer type.  Other callers of createInstruction might have different 
    requirements, and thus can manage the pointer to fit their needs.  Another idea would be to push the
   ownership to the RCU. 

    Currently, the FetchStage will wrap the Instruction
    pointer in a shared_ptr.  This allows us to remove the Instruction container in
    Backend, which was probably going to disappear, or move, at some point anyways.
    Note that I did run these changes through valgrind, to make sure we are not leaking
    memory.  While the shared_ptr comes with some additional overhead it relieves us
    from having to manage a list of generated instructions, and/or make lookup calls
    to remove the instructions. 

    I realize that both the Stage class and the Instruction pointer management
    (mentioned directly above) are separate but related ideas, and probably should
    land as separate patches; I am happy to do that if either idea is decent.
    The main reason these two ideas are together is that
    Stage::execute() can mutate an InstRef. For the fetch stage, the InstRef is populated
    as the primary action of that stage (execute()).  I didn't want to change the Stage interface
    to support the idea of generating an instruction.  Ideally, instructions are to
    be pushed through the pipeline.  I didn't want to draw too much of a
    specialization just for the fetch stage.  Excuse the word-salad.

Reviewers: andreadb, courbet, RKSimon

Reviewed By: andreadb

Subscribers: llvm-commits, mgorny, javed.absar, tschuett, gbedwell

Differential Revision: https://reviews.llvm.org/D46741

llvm-svn: 332390
2018-05-15 20:21:04 +00:00
Chandler Carruth
d9f1d49e26 [x86][eflags] Fix PR37431 by teaching the EFLAGS copy lowering to
specially handle SETB_C* pseudo instructions.

Summary:
While the logic here is somewhat similar to the arithmetic lowering, it
is different enough that it made sense to have its own function.
I actually tried a bunch of different optimizations here and none worked
well so I gave up and just always do the arithmetic based lowering.

Looking at code from the PR test case, we actually pessimize a bunch of
code when generating these. Because SETB_C* pseudo instructions clobber
EFLAGS, we end up creating a bunch of copies of EFLAGS to feed multiple
SETB_C* pseudos from a single set of EFLAGS. This in turn causes the
lowering code to ruin all the clever code generation that SETB_C* was
hoping to achieve. None of this is needed. Whenever we're generating
multiple SETB_C* instructions from a single set of EFLAGS we should
instead generate a single maximally wide one and extract subregs for all
the different desired widths. That would result in substantially better
code generation. But this patch doesn't attempt to address that.

The test case from the PR is included as well as more directed testing
of the specific lowering pattern used for these pseudos.

Reviewers: craig.topper

Subscribers: sanjoy, mcrosier, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D46799

llvm-svn: 332389
2018-05-15 20:16:57 +00:00
Benjamin Kramer
8996871624 Use perfect forwarding to deduplicate code in unit test. NFC.
llvm-svn: 332388
2018-05-15 20:08:15 +00:00
Konstantin Zhuravlyov
952e2e92b4 AMDGPU: Fix v_dot{4, 8}* instruction encoding
Differential Revision: https://reviews.llvm.org/D46848

llvm-svn: 332387
2018-05-15 19:32:47 +00:00
Martin Storsjo
059282774a [llvm-rc] Add support for the optional CLASS statement for dialogs
Differential Revision: https://reviews.llvm.org/D46875

llvm-svn: 332386
2018-05-15 19:21:28 +00:00
Michael Zolotukhin
041e33a699 [MemorySSA] Don't sort IDF blocks.
Summary:
After r332167 we started to sort the IDF blocks inside IDF calculation, so
there is no need to re-sort them on the user site. The test changes are due to
a slightly different order we're using now (originally we used DFSInNumber and
now the blocks are sorted by a pair (LevelFromRoot, DFSInNumber)).

Reviewers: dberlin, mgrang

Subscribers: Prazek, hiraditya, george.burgess.iv, llvm-commits

Differential Revision: https://reviews.llvm.org/D46899

llvm-svn: 332385
2018-05-15 18:40:29 +00:00
Andrea Di Biagio
5c841698f9 [llvm-mca] use a formatted_raw_ostream to insert padding and get rid of tabs. NFC
llvm-svn: 332381
2018-05-15 18:11:45 +00:00
Tom Stellard
12505c09c2 AMDGPU/GlobalISel: Implement select() for G_FCONSTANT
Summary: Also clean up G_CONSTANT selection.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D46170

llvm-svn: 332379
2018-05-15 17:57:09 +00:00
Konstantin Zhuravlyov
522efff244 AMDGPU: Add disasm tests for deep learning instructions + fix v_fmac_f32 disasm
Differential Revision: https://reviews.llvm.org/D46853

llvm-svn: 332377
2018-05-15 17:39:13 +00:00
Simon Pilgrim
54bcb07204 [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classes
BtVer2 - Fixes schedules for (V)CVTPS2PD instructions

A lot of the Intel models still have too many InstRW overrides for these new classes - this needs cleaning up but I wanted to get the classes in first

llvm-svn: 332376
2018-05-15 17:36:49 +00:00
Sanjay Patel
845a64cd77 [InstCombine] fix binop-of-shuffles to check uses
llvm-svn: 332375
2018-05-15 17:14:23 +00:00
Sanjay Patel
5d26412029 [InstCombine] add multi-use shuffle tests and regenerate checks; NFC
llvm-svn: 332373
2018-05-15 16:47:47 +00:00
Krzysztof Parzyszek
ff20ebbd68 [Hexagon] Remove unused function from subtarget
llvm-svn: 332369
2018-05-15 16:32:24 +00:00
Nico Weber
4581836d24 Rename three cxx files in unittests to cpp.
LLVM uses cpp as its C++ file extension, these are the only three cxx file in
the monorepo. These files apparently were called to escape a CMake check -- use
the LLVM_OPTIONAL_SOURCES mechanism that's meant as an escape for this case
instead.

No intended behavior change.
https://reviews.llvm.org/D46843

llvm-svn: 332368
2018-05-15 16:30:30 +00:00
Geoff Berry
4cf1405e34 [AArch64] Fix mir test case liveins info.
The test case added in r332265 had incomplete livein information which
was caught by the EXPENSIVE_CHECKS bot.  Fix the livein information and
add -verify-machineinstrs to the test case.

llvm-svn: 332367
2018-05-15 16:27:34 +00:00
Krzysztof Parzyszek
1f14705c5a [Hexagon] Remove unused flag from subtarget and (non)corresponding test
llvm-svn: 332365
2018-05-15 16:13:52 +00:00
Simon Dardis
161bbe8615 [mips] Mark select instructions correctly
Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46702

llvm-svn: 332364
2018-05-15 16:05:04 +00:00
Andrea Di Biagio
09c9c3e7d1 [llvm-mca] Strip leading tabs and spaces from instruction strings before printing. NFC
llvm-svn: 332361
2018-05-15 15:18:05 +00:00
Sanjay Patel
a66bd4e046 [DAG] propagate FMF for all FPMathOperators
This is a simple hack based on what's proposed in D37686, but we can extend it if needed in follow-ups. 
It gets us most of the FMF functionality that we want without adding any state bits to the flags. It 
also intentionally leaves out non-FMF flags (nsw, etc) to minimize the patch.

It should provide a superset of the functionality from D46563 - the extra tests show propagation and 
codegen diffs for fcmp, vecreduce, and FP libcalls.

The PPC log2() test shows the limits of this most basic approach - we only applied 'afn' to the last 
node created for the call. AFAIK, there aren't any libcall optimizations based on the flags currently, 
so that shouldn't make any difference.

Differential Revision: https://reviews.llvm.org/D46854

llvm-svn: 332358
2018-05-15 14:16:24 +00:00
Simon Pilgrim
3ab4e9e769 [X86] Split off F16C WriteCvtPH2PS/WriteCvtPS2PH scheduler classes
Btver2 - VCVTPH2PSYrm needs to double pump the AGU
Broadwell - missing VCVTPS2PH*mr stores extra latency

Allows us to remove the WriteCvtF2FSt conversion store class

llvm-svn: 332357
2018-05-15 14:12:32 +00:00
Paul Semel
0a67d7e1d5 [llvm-objcopy] Add --keep-symbol (-K) option
This option permits to explicitly keep the specified
symbol so that it doesn't get removed.

Differential Revision: https://reviews.llvm.org/D46819

llvm-svn: 332356
2018-05-15 14:09:37 +00:00
Eric Liu
7dbebcbfed Fix broken asan Support tests
The asan failures were caught in google internal asan tests after r332311
o Make StackOption support cl::list
o Rememeber to removeArguments for cl::alias in tests.

llvm-svn: 332354
2018-05-15 13:43:20 +00:00
Pavel Labath
861585e381 Reapply "DWARFVerifier: Check "completeness" of .debug_names section"
This is a resubmit of r331868 (D46583), which was reverted due to
failures on the PS4 bot.

These have been resolved with r332246/D46748.

llvm-svn: 332349
2018-05-15 13:24:10 +00:00
Clement Courbet
592a4a5772 [llvm-exegesis] Split AsmTemplate.Name into components.
Summary:
AsmTemplate becomes IntructionBenchmarkKey, which has three components.
This allows retreiving the opcode for analysis.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D46873

llvm-svn: 332348
2018-05-15 13:07:05 +00:00
Simon Pilgrim
0428676677 [llvm-mca][x86] Add F16C instruction tests
llvm-svn: 332347
2018-05-15 12:50:06 +00:00
Clement Courbet
6c83d875a3 Fix compilation under pre-c++14 gccs.
llvm-svn: 332346
2018-05-15 12:38:06 +00:00
Clement Courbet
d1aa19fac3 Fix r332344: only the native target is linked.
llvm-svn: 332345
2018-05-15 12:27:36 +00:00
Clement Courbet
be6ab91eb0 [llvm-exegesis] Add an analysis mode.
Summary:
The analysis mode gives the user a clustered view of the measurement results.
Next steps are (requires the split ok AsmTemplate.Name into {mnemonic, mode}):
 - Show the sched class.
 - Highlight any inconsistencies with the checked-in data.

Reviewers: gchatelet

Subscribers: mgorny, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D46865

llvm-svn: 332344
2018-05-15 12:08:00 +00:00
whitequark
c0e7687557 [MergeFunctions] Fix merging of small weak functions
When two interposable functions are merged, we cannot replace
uses and have to emit calls to a common internal function. However,
writeThunk() will not actually emit a thunk if the function is too
small. This leaves us in a broken state where mergeTwoFunctions
already rewired the functions, but writeThunk doesn't do anything.

This patch changes the implementation so that:

 * writeThunk() does just that.
 * The direct replacement of calls is moved into mergeTwoFunctions()
   into the non-interposable case only.
 * isThunkProfitable() is extracted and will be called for
   the non-iterposable case always, and in the interposable case
   only if uses are still left after replacement.

This issue has been introduced in https://reviews.llvm.org/D34806,
where the code for checking thunk profitability has been moved.

Differential Revision: https://reviews.llvm.org/D46804

Reviewed By: whitequark

llvm-svn: 332342
2018-05-15 11:31:07 +00:00
Simon Dardis
5ffec4099c [mips] Fix formatting of floating point conversion patterns
llvm-svn: 332341
2018-05-15 11:21:07 +00:00
Simon Dardis
875f23c329 [mips] Add disassembly support for comparison instructions
llvm-svn: 332340
2018-05-15 11:18:24 +00:00