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Commit Graph

164 Commits

Author SHA1 Message Date
Eric Christopher
f1bb5da020 Have the X86 backend use Triple instead of a string and some enums.
llvm-svn: 107625
2010-07-05 19:26:33 +00:00
Chris Lattner
3fd8e8a2f5 fix a nasty bug where we were not treating available_externally
symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.

llvm-svn: 105954
2010-06-14 20:11:56 +00:00
Dan Gohman
ba64544096 FastISel doesn't yet handle callee-pop functions.
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.

llvm-svn: 104866
2010-05-27 18:43:40 +00:00
Evan Cheng
d4fe387eb8 Enable i16 to i32 promotion by default.
llvm-svn: 102493
2010-04-28 08:30:49 +00:00
Evan Cheng
0f4671b0dd isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
llvm-svn: 101979
2010-04-21 01:47:12 +00:00
Eric Christopher
bbf4e35cf6 Separate out the AES-NI instructions from the SSE4.2 instructions. Add
a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.

llvm-svn: 100231
2010-04-02 21:54:27 +00:00
Evan Cheng
e60ac0f6a6 Nehalem unaligned memory access is fast.
llvm-svn: 100089
2010-04-01 05:58:17 +00:00
Evan Cheng
5ace6fffac Turning off post-ra scheduling for x86. It isn't a consistent win.
llvm-svn: 98810
2010-03-18 06:55:42 +00:00
Chris Lattner
1b5fdcde7a no really, all 64-bit cpu's have cmov support. This should
fix the rest of the buildbot failures on non-x86 hosts.

llvm-svn: 98522
2010-03-14 22:39:35 +00:00
Jeffrey Yasskin
fb10587e50 Kill ModuleProvider and ghost linkage by inverting the relationship between
Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.

Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods.  The bindings to
other languages still use the ModuleProvider concept.  It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.

Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735.

llvm-svn: 94686
2010-01-27 20:34:15 +00:00
David Greene
b879ff4855 Implement a feature (-vector-unaligned-mem) to allow targets to
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.

llvm-svn: 93151
2010-01-11 16:29:42 +00:00
David Greene
8a947405d5 Change errs() to dbgs().
llvm-svn: 92648
2010-01-05 01:29:13 +00:00
Evan Cheng
7cd6bfe549 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
llvm-svn: 91910
2009-12-22 17:47:23 +00:00
Evan Cheng
d97d025eba On recent Intel u-arch's, folding loads into some unary SSE instructions can
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672
2009-12-18 07:40:29 +00:00
Dan Gohman
44e25ed254 Don't enable the post-RA scheduler on x86 except at -O3. In its
current form, it is too expensive in compile time.

llvm-svn: 90781
2009-12-07 19:04:31 +00:00
Dan Gohman
3517f425b8 Target-independent support for TargetFlags on BlockAddress operands,
and support for blockaddresses in x86-32 PIC mode.

llvm-svn: 89506
2009-11-20 23:18:13 +00:00
Daniel Dunbar
59040c2825 Add llvm::sys::getHostCPUName, for detecting the LLVM name for the host CPU.
- This is an initial step towards -march=native support in Clang, and towards
   eliminating host dependencies in the targets. See PR5389.

 - Patch by Roman Divacky!

llvm-svn: 88768
2009-11-14 10:09:12 +00:00
David Goodwin
e1d06f2239 Allow target to specify regclass for which antideps will only be broken along the critical path.
llvm-svn: 88682
2009-11-13 19:52:48 +00:00
David Goodwin
93a4f29c67 Fixed to address code review. No functional changes.
llvm-svn: 86634
2009-11-10 00:48:55 +00:00
Evan Cheng
0a57c7d459 Remove X86Subtarget::IsLinux. It's no longer being used.
llvm-svn: 84200
2009-10-15 20:23:21 +00:00
Evan Cheng
41e87f2f13 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
llvm-svn: 80904
2009-09-03 07:04:02 +00:00
Daniel Dunbar
80f8fc8a2a Make these functions static and local.
llvm-svn: 80892
2009-09-03 05:47:34 +00:00
Evan Cheng
6d2d69faf9 X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.
No functionality changes.

llvm-svn: 80880
2009-09-03 04:37:05 +00:00
Chris Lattner
c66a43e2b0 Add support for modeling whether or not the processor has support for
conditional moves as a subtarget feature.  This is the easy part of 
PR4841.

llvm-svn: 80763
2009-09-02 05:53:04 +00:00
Anton Korobeynikov
8595d8549f Short-term workaround for frame-related weirdness on win64.
Some other minor win64 fixes as well.

Patch by Michael Beck!

llvm-svn: 80370
2009-08-28 16:06:41 +00:00
Chris Lattner
c2a229453e change the -x86-asm-syntax=intel/att flag to be in X86TAI
instead of X86 Subtarget.  This elimianates dependencies on
X86Subtarget from X86TAI.

llvm-svn: 78746
2009-08-11 23:01:09 +00:00
Daniel Dunbar
3d2ac751da Remove some dead code.
llvm-svn: 78219
2009-08-05 18:12:37 +00:00
Bill Wendling
b8e74aab37 - s/DOUT/DEBUG(errs()/g
- Tidy up some headers.

llvm-svn: 77929
2009-08-03 00:11:34 +00:00
Daniel Dunbar
0b82c938fe Normalize Subtarget constructors to take a target triple string instead of
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918
2009-08-02 22:11:08 +00:00
Daniel Dunbar
8be4e61a2d Fix some minor MSVC compiler warnings.
llvm-svn: 76356
2009-07-19 01:38:38 +00:00
Evan Cheng
e9dc6cf3b1 GV with ghost linkage (module being lazily streamed in in JIT lazy compilation mode) do not require extra load from stub. This fixes ExecutionEngine/2005-12-02-TailCallBug.ll.
llvm-svn: 76121
2009-07-16 22:53:10 +00:00
Chris Lattner
4b7ff8e0c0 fix indentation
llvm-svn: 75277
2009-07-10 21:01:59 +00:00
Chris Lattner
478fc8442b remove the now-dead TM argument to these methods.
llvm-svn: 75276
2009-07-10 21:00:45 +00:00
Chris Lattner
9c13214ee8 make PIC vs DynamicNoPIC be explicit in PICStyles.
llvm-svn: 75275
2009-07-10 20:58:47 +00:00
Chris Lattner
933108f921 some minor simplifications.
llvm-svn: 75274
2009-07-10 20:53:38 +00:00
Chris Lattner
9deef50410 add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.
llvm-svn: 75273
2009-07-10 20:47:30 +00:00
Chris Lattner
6097f82e18 simplify fast isel by using ClassifyGlobalReference. This
elimiantes the last use of GVRequiresExtraLoad, so delete it.

llvm-svn: 75244
2009-07-10 07:48:51 +00:00
Chris Lattner
7c038a2b3c eliminate GVRequiresRegister, replacing it with predicates we
need for other purposes.

llvm-svn: 75243
2009-07-10 07:38:24 +00:00
Chris Lattner
0cae8c7845 move some classification logic around. Now GVRequiresExtraLoad
is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.

llvm-svn: 75237
2009-07-10 07:20:05 +00:00
Chris Lattner
41fccd30b7 GVRequiresExtraLoad is now never used for calls, simplify it based on this.
llvm-svn: 75232
2009-07-10 05:52:02 +00:00
Chris Lattner
832a724072 actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code
more complex and slow than just directly testing what we care about.

llvm-svn: 75231
2009-07-10 05:48:03 +00:00
Chris Lattner
2161376696 There is only one case where GVRequiresExtraLoad returns true for calls:
split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.

llvm-svn: 75230
2009-07-10 05:45:15 +00:00
Chris Lattner
2e5e403f53 the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it.
llvm-svn: 75229
2009-07-10 05:37:11 +00:00
Chris Lattner
76adfe755d simplify some code based on the fact that picstyles != none are only valid
in pic or dynamic-no-pic mode. Also, x86-64 never used picstylegot.

llvm-svn: 75101
2009-07-09 04:39:06 +00:00
Chris Lattner
b5ce27ffe6 Reduce indentation in GVRequiresExtraLoad. Return true for windows
with DLLImport symbols even when in -static mode.

llvm-svn: 75093
2009-07-09 03:27:27 +00:00
David Greene
d33e8e7d83 Add feature flags for AVX and FMA and fix some SSE4A feature flag
initialization problems.

llvm-svn: 74350
2009-06-26 22:46:54 +00:00
Anton Korobeynikov
d08df21f36 The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

llvm-svn: 73095
2009-06-08 22:53:56 +00:00
Stefanus Du Toit
031dcf315f Update CPU capabilities for AMD machines
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10

New processor names match those used by gcc.

Patch by Paul Redmond!

llvm-svn: 72434
2009-05-26 21:04:35 +00:00
Evan Cheng
e17c02e328 Try again. Allow call to immediate address for ELF or when in static relocation mode.
llvm-svn: 72160
2009-05-20 04:53:57 +00:00
Chris Lattner
b47e34ac59 add support for detecting process features on win64, patch by
Nicolas Capens!

llvm-svn: 70057
2009-04-25 18:27:23 +00:00