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Commit Graph

1974 Commits

Author SHA1 Message Date
John McCall
8ee507f0f5 Silence a clang warning about the deprecated (but perfectly reasonable in
context) increment-of-bool idiom.

llvm-svn: 91564
2009-12-16 20:31:50 +00:00
Jim Grosbach
666c19db99 Mark STREX* as earlyclobber for the success result register.
llvm-svn: 91555
2009-12-16 19:44:06 +00:00
Johnny Chen
7339b74117 Add encoding bits for some Thumb instructions. Plus explicitly set the top two
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496
2009-12-16 02:32:54 +00:00
John McCall
e3df19422d Every anonymous namespace is different. Caught by clang++.
llvm-svn: 91481
2009-12-16 00:15:28 +00:00
Jeffrey Yasskin
d50951dc1e Change indirect-globals to use a dedicated allocIndirectGV. This lets us
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.

llvm-svn: 91464
2009-12-15 22:42:46 +00:00
Johnny Chen
8ef481b5d7 Added encoding bits for the Thumb ISA. Initial checkin.
llvm-svn: 91434
2009-12-15 17:24:14 +00:00
Jim Grosbach
76d722dd6c nand atomic requires opposite operand ordering
llvm-svn: 91371
2009-12-15 00:12:35 +00:00
Johnny Chen
61b6d221d2 Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate
between BR_JTr and STREXD.

llvm-svn: 91339
2009-12-14 21:51:34 +00:00
Jim Grosbach
dc0006c895 v6 sync insn copy/paste error
llvm-svn: 91333
2009-12-14 21:33:32 +00:00
Jim Grosbach
09167e5bbb Add ARMv6 memory and sync barrier instructions
llvm-svn: 91329
2009-12-14 21:24:16 +00:00
Johnny Chen
80b7b55eea Fixed encoding bits typo of ldrexd/strexd.
llvm-svn: 91327
2009-12-14 21:01:46 +00:00
Jim Grosbach
266c2d59e6 Thumb2 atomic operations
llvm-svn: 91321
2009-12-14 20:14:59 +00:00
Jim Grosbach
c7285dc721 correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
llvm-svn: 91313
2009-12-14 19:24:11 +00:00
Jim Grosbach
723a7aa4e9 add Thumb2 atomic and memory barrier instruction definitions
llvm-svn: 91310
2009-12-14 18:56:47 +00:00
Jim Grosbach
99ace7c9ff whitespace
llvm-svn: 91307
2009-12-14 18:36:32 +00:00
Jim Grosbach
aaf39891f4 ARM memory barrier instructions are not predicable
llvm-svn: 91305
2009-12-14 18:31:20 +00:00
Jim Grosbach
5741d33c74 add ldrexd/strexd instructions
llvm-svn: 91284
2009-12-14 17:02:55 +00:00
Jim Grosbach
87975f6229 atomic binary operations up to 32-bits wide.
llvm-svn: 91260
2009-12-14 04:22:04 +00:00
Jim Grosbach
187ad02a4f Framework for atomic binary operations. The emitter for the pseudo instructions
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200
2009-12-12 01:40:06 +00:00
Jim Grosbach
0cfc544e97 memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.
llvm-svn: 91150
2009-12-11 20:29:53 +00:00
Johnny Chen
5d6f117ed5 Store Register Exclusive should leave the source register Inst{3-0} unspecified.
llvm-svn: 91143
2009-12-11 19:37:26 +00:00
Jim Grosbach
89e51fb5ff Update properties.
llvm-svn: 91140
2009-12-11 18:52:41 +00:00
Jim Grosbach
5a1c16e5bb Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
llvm-svn: 91090
2009-12-11 01:42:04 +00:00
Jim Grosbach
608ef114aa Add instruction encoding for DMB/DSB
llvm-svn: 91053
2009-12-10 18:35:32 +00:00
Jim Grosbach
be89da9845 Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
llvm-svn: 91003
2009-12-10 00:11:09 +00:00
Evan Cheng
edcc21919f - Support inline asm 'w' constraint for 128-bit vector types.
- Also support the 'q' NEON registers asm code.

llvm-svn: 90894
2009-12-08 23:06:22 +00:00
Anton Korobeynikov
eee906f4f0 Dynamic stack realignment use of sp register as source/dest register
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

llvm-svn: 90724
2009-12-06 22:39:50 +00:00
Dan Gohman
f9654e9258 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634
2009-12-05 00:44:40 +00:00
Jim Grosbach
891c545129 remove out of date FIXME.
llvm-svn: 90490
2009-12-03 21:55:01 +00:00
Chris Lattner
b3cc713378 fix a build problem with VC++, PR5664, patch by Alp Toker!
llvm-svn: 90419
2009-12-03 06:58:32 +00:00
Bob Wilson
b53c801366 Recognize canonical forms of vector shuffles where the same vector is used for
both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.

llvm-svn: 90417
2009-12-03 06:40:55 +00:00
Chris Lattner
9ce833945e improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!

llvm-svn: 90365
2009-12-03 00:50:42 +00:00
Jim Grosbach
0e1230b23b Factor the stack alignment calculations out into a target independent pass.
No functionality change.

llvm-svn: 90336
2009-12-02 19:30:24 +00:00
Jim Grosbach
5541b5f793 Thumb1 exception handling setjmp
llvm-svn: 90246
2009-12-01 18:10:36 +00:00
Johnny Chen
e3171163da For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
llvm-svn: 90243
2009-12-01 17:37:06 +00:00
Johnny Chen
7f7f23087c For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.

Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
2009-12-01 00:02:02 +00:00
Bob Wilson
b293fe32cb Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low.  The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.

llvm-svn: 90144
2009-11-30 18:35:03 +00:00
Bob Wilson
f893a19df9 Fix some more ARM unified syntax warnings.
llvm-svn: 90141
2009-11-30 17:47:19 +00:00
Bob Wilson
c5fa56c805 Refactor target hook for tail duplication as requested by Chris.
Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation.  I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size.  ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.

llvm-svn: 89814
2009-11-24 23:35:49 +00:00
Evan Cheng
b81878ed80 Enable predication of NEON instructions in Thumb2 mode.
llvm-svn: 89748
2009-11-24 08:06:15 +00:00
Evan Cheng
179a11776c Data type suffix must come after predicate.
llvm-svn: 89723
2009-11-24 01:05:23 +00:00
Anton Korobeynikov
0f885eb7fd Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
2009-11-24 00:44:37 +00:00
Jim Grosbach
a142a709c8 80 column violations
llvm-svn: 89718
2009-11-24 00:20:27 +00:00
Jeffrey Yasskin
0a0b21f8c5 * Move stub allocation inside the JITEmitter, instead of exposing a
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816.

* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.

llvm-svn: 89715
2009-11-23 23:35:19 +00:00
Dan Gohman
b5ec39e2dc Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711
2009-11-23 23:20:51 +00:00
Jeffrey Yasskin
ed6d1ce9ae Allow more than one stub to be being generated at the same time.
It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.

llvm-svn: 89708
2009-11-23 22:49:00 +00:00
Evan Cheng
8c9f6147cd Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.

llvm-svn: 89706
2009-11-23 21:57:23 +00:00
Jim Grosbach
76b545e988 move fconst[sd] to UAL. <rdar://7414913>
llvm-svn: 89700
2009-11-23 21:08:25 +00:00
Johnny Chen
e59a67f527 Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup.  VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.

llvm-svn: 89699
2009-11-23 21:00:43 +00:00
Jim Grosbach
bbb786facf fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
llvm-svn: 89694
2009-11-23 20:35:53 +00:00