1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-25 05:52:53 +02:00
Commit Graph

2518 Commits

Author SHA1 Message Date
Craig Topper
9d32602cfd Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
Craig Topper
7b5028ec10 Fix typo in r140954.
llvm-svn: 140962
2011-10-02 04:54:26 +00:00
Craig Topper
43fd621df8 Fix disassembling of INVEPT and INVVPID to take operands
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
Craig Topper
99ad3cc23e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
Peter Collingbourne
01246536d9 Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
2011-10-01 16:41:13 +00:00
Bob Wilson
270da20c9e Subtarget getFeatureBits() returns a uint64_t, not unsigned.
llvm-svn: 140928
2011-10-01 02:47:54 +00:00
Jakob Stoklund Olesen
05823401a6 Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().
All the sub-class bit vectors are computed when first creating the
register bank.

llvm-svn: 140905
2011-09-30 23:47:05 +00:00
Jakob Stoklund Olesen
010e9bb778 Store sub-class lists as a bit vector.
This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898
2011-09-30 22:19:07 +00:00
Jakob Stoklund Olesen
4c57e66252 Extract a slightly more general BitVector printer.
This one can also print 32-bit groups.

llvm-svn: 140897
2011-09-30 22:18:54 +00:00
Jakob Stoklund Olesen
402aa89d8a Compute lists of super-classes in CodeGenRegisterClass.
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

llvm-svn: 140895
2011-09-30 22:18:45 +00:00
David Greene
2d3533a153 Implement VarListElementInit:: resolveListElementReference
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

llvm-svn: 140882
2011-09-30 20:59:49 +00:00
Jakob Stoklund Olesen
82a55057c4 Precompute a bit vector of register sub-classes.
llvm-svn: 140827
2011-09-30 00:10:40 +00:00
Jakob Stoklund Olesen
35c649f61b Order register classes topologically.
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

llvm-svn: 140826
2011-09-30 00:10:36 +00:00
Jakob Stoklund Olesen
d7b6708541 Switch to ArrayRef<CodeGenRegisterClass*>.
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816
2011-09-29 22:28:37 +00:00
Daniel Dunbar
d499233312 tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and
"show-in-system-header" bits, which I will be adding in Clang shortly.

llvm-svn: 140741
2011-09-29 00:29:04 +00:00
Owen Anderson
7742c81cde ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
llvm-svn: 140560
2011-09-26 21:06:22 +00:00
Jakob Stoklund Olesen
cbd2c336ab Add target hook for pseudo instruction expansion.
Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

llvm-svn: 140472
2011-09-25 19:21:35 +00:00
Craig Topper
655f8a01e6 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
llvm-svn: 140370
2011-09-23 06:57:25 +00:00
Andrew Trick
bfac89c238 Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160
2011-09-20 18:22:31 +00:00
Andrew Trick
53aeb9f663 ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134
2011-09-20 03:17:40 +00:00
Eric Christopher
6cf9c3efe8 Remove more of llvmc and dependencies.
llvm-svn: 140121
2011-09-20 00:34:27 +00:00
Jim Grosbach
6da9e6b23d Thumb2 assembly parsing and encoding for TBB/TBH.
llvm-svn: 140078
2011-09-19 22:21:13 +00:00
David Greene
799578fee4 Better Error Reporting
Report missing template arguments more helpfully by supplying the name
of the missing argument in the error message.

llvm-svn: 140034
2011-09-19 18:26:07 +00:00
Craig Topper
60719c7bfb Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
llvm-svn: 139691
2011-09-14 06:41:26 +00:00
Argyrios Kyrtzidis
d0acbd50a7 [tablegen] In ClangAttrEmitter.cpp handle SourceLocation arguments to attributes.
llvm-svn: 139617
2011-09-13 18:41:43 +00:00
Argyrios Kyrtzidis
56cc934d76 In ClangAttrEmitter.cpp emit code that allows attributes to keep their source range.
llvm-svn: 139598
2011-09-13 16:05:43 +00:00
Craig Topper
03c833ff84 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
llvm-svn: 139588
2011-09-13 06:54:58 +00:00
Craig Topper
a9b27eecc9 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
llvm-svn: 139485
2011-09-11 21:41:45 +00:00
Craig Topper
8361de67b5 Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
llvm-svn: 139484
2011-09-11 20:23:20 +00:00
Douglas Gregor
6a808433ce Update Clang AST attribute reader tblgen generation to match with ASTReader change
llvm-svn: 139414
2011-09-09 21:37:29 +00:00
Jim Grosbach
eb2d668899 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
Eli Friedman
fd4451674b Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection.
llvm-svn: 139317
2011-09-08 21:00:31 +00:00
Caitlin Sadowski
ac6881fc85 Added LateParsed property to TableGen attributes.
This patch was written by DeLesley Hutchins.

llvm-svn: 139300
2011-09-08 17:40:49 +00:00
James Molloy
090d019a29 Fix warning on windows; use of comparison with bool argument.
llvm-svn: 139286
2011-09-08 08:12:01 +00:00
Andrew Trick
dc3f981b08 Fix a use of freed string contents.
Speculatively try to fix our windows testers with a patch I found on the internet.

llvm-svn: 139279
2011-09-08 05:25:49 +00:00
Andrew Trick
daeb007cee whitespace
llvm-svn: 139278
2011-09-08 05:23:14 +00:00
Jim Grosbach
8b54d19514 Thumb2 assembly parsing and encoding for LDRBT.
llvm-svn: 139267
2011-09-07 23:39:14 +00:00
Jim Grosbach
20642fb479 Thumb2 parsing and encoding for LDR(immediate).
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254
2011-09-07 20:58:57 +00:00
James Molloy
ac057f13a5 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
Joerg Sonnenberger
9fa9ed6961 Dependency should be on the output file name, not the dependency file
name.

llvm-svn: 139220
2011-09-07 02:12:03 +00:00
David Greene
9cb3b3dd2e Make RecordVal Name an Init
Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names.  We'll use this to
provide more programmability in how we name defs and their associated
members.

llvm-svn: 139031
2011-09-02 20:12:07 +00:00
Kevin Enderby
edfcba2f3c Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
Craig Topper
316c7bfe37 Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
llvm-svn: 138997
2011-09-02 04:17:54 +00:00
James Molloy
4a63186421 Fix up r137380 based on post-commit review by Jim Grosbach.
llvm-svn: 138948
2011-09-01 18:02:14 +00:00
Evan Cheng
91aa81acaa Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810
2011-08-30 19:09:48 +00:00
Craig Topper
5556444bf7 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
llvm-svn: 138795
2011-08-30 07:09:35 +00:00
Kevin Enderby
f1aef98ad2 Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
llvm-svn: 138771
2011-08-29 22:06:28 +00:00
Owen Anderson
fd21da3506 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
Craig Topper
5af7ba783d Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
llvm-svn: 138552
2011-08-25 07:42:00 +00:00
Jim Grosbach
b2b155a93f Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
2011-08-24 21:22:15 +00:00
Jim Grosbach
b33129ebad Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.

llvm-svn: 138445
2011-08-24 17:46:13 +00:00
Caitlin Sadowski
9a011eafa9 Thread safety: Adding in an option for variadic expr* array of arguments
llvm-svn: 138351
2011-08-23 18:49:23 +00:00
Eric Christopher
cd47076a67 Fix fpimmm->fpimm typo.
Patch by Micah Villmow!

llvm-svn: 138330
2011-08-23 15:42:35 +00:00
Jim Grosbach
4e811b51eb Allow non zero_reg explicit values for OptionalDefOperands in aliases.
llvm-svn: 138073
2011-08-19 20:33:06 +00:00
Jim Grosbach
d990119d89 Tidy up. Formatting.
llvm-svn: 138067
2011-08-19 19:53:51 +00:00
Owen Anderson
3146968039 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

llvm-svn: 137830
2011-08-17 17:44:15 +00:00
Jim Grosbach
3f1d3ff1d4 Prefer diagnostics from target predicate in asm matcher.
llvm-svn: 137742
2011-08-16 20:12:35 +00:00
Bob Wilson
b9df018555 Avoid evaluating Neon macro arguments more than once by disabling type checks.
It turns out that the use of "__extension__" in these macros was disabling
the expected "incompatible pointer" warnings, so these type checks were not
doing anything anyway.  They introduced a serious bug by evaluating some
macro arguments twice, which is a big problem for arguments with side effects.
I'll have to find another way to get the right type checking.  Radar 9947657.

llvm-svn: 137680
2011-08-15 23:22:56 +00:00
Jim Grosbach
31c0c9a1f6 MCTargetAsmParser target match predicate support.
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675
2011-08-15 23:03:29 +00:00
Jim Grosbach
bc7725aa09 Move MatchResultTy enum into base class definition.
No need for it to be redefined as part of every derived target asm parser
class.

llvm-svn: 137649
2011-08-15 20:53:08 +00:00
David Greene
2c065bce0c Make Record Name an Init
Use an Init (ultimately a StringInit) to represent the Record name.
This allows the name to be composed by standard TableGen operators.
This will enable us to get rid of the ugly #NAME# hack processing and
naturally replace it with operators.  It also increases flexibility
and power of the TableGen language by allowing record identifiers to
be computed dynamically.

llvm-svn: 137232
2011-08-10 18:27:46 +00:00
David Greene
1b84fa8ef7 Add getAsUnquotedString
Add a method to return an Init as an unquoted string.  This primarily
affects StringInit where we return the value without surrounding it
with quotes.

This is in preparation for removing the ugly #NAME# hack and replacing
it with standard TabelGen operators.

llvm-svn: 137231
2011-08-10 18:27:45 +00:00
Owen Anderson
c85618de24 Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings.
llvm-svn: 137171
2011-08-09 23:05:23 +00:00
Owen Anderson
8ad37f68a2 Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Owen Anderson
ffe1c55752 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Owen Anderson
e4638b5b2d Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
llvm-svn: 137062
2011-08-08 20:42:17 +00:00
Owen Anderson
1136bcc11e LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
llvm-svn: 136896
2011-08-04 18:24:14 +00:00
Jim Grosbach
767e9d16e6 ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Jim Grosbach
138b79f1ea ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.

llvm-svn: 136704
2011-08-02 18:07:32 +00:00
Owen Anderson
00a562a5c5 Make the FixedLengthDecoderEmitter smart enough to autogenerate decoders for encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers.
llvm-svn: 136660
2011-08-01 22:45:43 +00:00
Owen Anderson
167040246a The FixedLenDecoder needs to gracefully handle failing per-instruction decoder hooks in addition to per-operand decoder hooks.
llvm-svn: 136645
2011-08-01 20:06:49 +00:00
Owen Anderson
703d9b30bf Enhance the fixed length disassembler to better handle operand decoding failures.
llvm-svn: 136635
2011-08-01 18:44:37 +00:00
Owen Anderson
f946892d3e Correctly handle scattered operands where the bits of the operand are contiguous, but out of order.
llvm-svn: 136534
2011-07-29 23:01:18 +00:00
David Greene
43a26c71e8 Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
2011-07-29 22:43:06 +00:00
David Greene
6544f815c3 Remove a blank line from the top.
llvm-svn: 136511
2011-07-29 20:50:18 +00:00
David Greene
944f1cc9a6 [AVX] Make DagInits Unique
Make sure DagInits are unique and created only once.

llvm-svn: 136501
2011-07-29 19:07:26 +00:00
David Greene
e1cb4aa5bb [AVX] Make FieldInit Unique
Make sure FieldInits are unique and created only once.

llvm-svn: 136500
2011-07-29 19:07:24 +00:00
David Greene
619a865a18 [AVX] Make VarListElementInit Unique
Make sure VarListElementInits are unique and created only once.

llvm-svn: 136499
2011-07-29 19:07:23 +00:00
David Greene
488cb6519c [AVX] Make VarBitInit Unique
Make sure VarBitInits are unique and created only once.

llvm-svn: 136498
2011-07-29 19:07:22 +00:00
David Greene
c941c167b2 [AVX] Make VarInit Unique
Make sure VarInits are unique and created only once.

llvm-svn: 136497
2011-07-29 19:07:21 +00:00
David Greene
cb87febe43 [AVX] Make TernOpInit Unique
Make sure TernOpInits are unique and created only once.  This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.

llvm-svn: 136496
2011-07-29 19:07:20 +00:00
David Greene
b561cf4112 [AVX] Make BinOpInit Unique
Make sure BinOpInits are unique and created only once.  This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.

llvm-svn: 136495
2011-07-29 19:07:19 +00:00
David Greene
9ee3433c62 [AVX] Make UnOpInit Unique
Make sure UnOpInits are unique and created only once.  This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.

llvm-svn: 136494
2011-07-29 19:07:18 +00:00
David Greene
d7910a0936 [AVX] Make ListInits Unique
Ensure ListInits are unique and only created once.  This will be
important for AVX as lists will be used extensively to pass generic
patterns, prefix information and other things to lower-level
pattern-generation classes.

llvm-svn: 136493
2011-07-29 19:07:16 +00:00
David Greene
94607ffc67 [AVX] Make CodeInit Unique
Use a StringMap to ensure CodeInits are unique and created only
once.

llvm-svn: 136492
2011-07-29 19:07:15 +00:00
David Greene
94a66246c5 [AVX] Make StringInit Unique
Use a StringMap to ensure the StringInits are unique.  This is
especially important for AVX where we will have many smallish
strings representing instruction prefixes, suffixes and the like.

llvm-svn: 136491
2011-07-29 19:07:14 +00:00
David Greene
b6f328122b [AVX] Make IntInit Unique
Use a DenseMap to make sure only one IntInit of any value exists.

llvm-svn: 136490
2011-07-29 19:07:12 +00:00
David Greene
a527d6a682 [AVX] Make BitsInit Unique
Make BitsInit a FoldingSetNode so we can unique it.

llvm-svn: 136489
2011-07-29 19:07:11 +00:00
David Greene
65994da789 [AVX] Unique BitInit
Keep only two copies of BitInit: one for true and one for false.

llvm-svn: 136488
2011-07-29 19:07:10 +00:00
David Greene
0f35a5d4aa [AVX] Unique UnsetInit
Keep only one UnsetInit around.

llvm-svn: 136487
2011-07-29 19:07:09 +00:00
David Greene
88abfb940e [AVX] Create Inits Via Factory Method
Replace uses of new *Init with *Init::get.  This hides the allocation
implementation so that we can unique Inits in various ways.

llvm-svn: 136486
2011-07-29 19:07:07 +00:00
David Greene
b149019c5d [AVX] Constify Inits
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
2011-07-29 19:07:05 +00:00
David Greene
b22fe7cc2b [AVX] Remove non-const Iterators
Remove all non-const iterators from Init classes.  This is another
step toward constifying Inits and ultimately turning them into
FoldingSetNodes.

llvm-svn: 136484
2011-07-29 19:07:02 +00:00
David Greene
9f9d96009a [AVX] Remove Mutating Members from Inits
Get rid of all Init members that modify internal state.  This is in
preparation for making references to Inits const.

llvm-svn: 136483
2011-07-29 19:07:00 +00:00
David Greene
65a7b1b235 Add ListInit::getValues
Add a getValues ListInit method to return the sequence of values in
the list.

llvm-svn: 136482
2011-07-29 19:06:59 +00:00
David Greene
5927323d9c Add a std::string Wrapper for TableGen
Create a std::string wrapper for use as a DenseMap key.  DenseMap is
not safe in generate with strings, so this wrapper indicates that only
strings guaranteed not to have certain values should be used in the
DenseMap.

llvm-svn: 136481
2011-07-29 19:06:58 +00:00
Owen Anderson
b651954088 Third time's the charm for implementing tied operand decoding properly.
llvm-svn: 136478
2011-07-29 18:28:52 +00:00
Owen Anderson
b905884f67 Fix a case where, when trying to track tied operands, we'd accidentally overwrite our mapping.
llvm-svn: 136467
2011-07-29 17:32:03 +00:00
Owen Anderson
8e67a44e7c Enhance the fixed-length decoder emitter to support tied operands.
llvm-svn: 136431
2011-07-28 23:56:20 +00:00
Owen Anderson
3650feb7f7 Enhance the fixed-length decoder emitter to support parsing scattered fields.
llvm-svn: 136405
2011-07-28 21:54:31 +00:00