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5711 Commits

Author SHA1 Message Date
Eric Christopher
8ffa64fdb5 Temporarily revert r56550 until missing commit can be added. 
llvm-svn: 56551
 2008-09-24 08:30:44 +00:00
Bill Wendling
456b33b615 Refactor the constant folding code into it's own function. And call it from both 
the SelectionDAG and DAGCombiner code. The only functionality change is that now
the DAG combiner is performing the constant folding for these operations instead
of being a no-op.

This is *not* in response to a bug, so there isn't a testcase.

llvm-svn: 56550
 2008-09-24 07:11:26 +00:00
Dale Johannesen
bc29bec7f8 Next round of earlyclobber handling. Approach the 
RA problem by expanding the live interval of an
earlyclobber def back one slot.  Remove
overlap-earlyclobber throughout.  Remove 
earlyclobber bits and their handling from
live internals.

llvm-svn: 56539
 2008-09-24 01:07:17 +00:00
Dan Gohman
a7a04d8ae6 Refactor the logic for testing if an instruction is dead into a 
separate method.

llvm-svn: 56531
 2008-09-24 00:27:38 +00:00
Dan Gohman
49becd6c31 Set SetStore to false, to allow this pass to delete 
dead loads.

llvm-svn: 56529
 2008-09-24 00:07:08 +00:00
Dan Gohman
0cf7b31c69 Add a method to MachineInstr for testing whether it makes 
any volatile memory references.

llvm-svn: 56528
 2008-09-24 00:06:15 +00:00
Evan Cheng
f942615847 Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc. 
llvm-svn: 56526
 2008-09-24 00:05:32 +00:00
Devang Patel
a3e9bf1bca s/ParameterAttributes/Attributes/g 
llvm-svn: 56513
 2008-09-23 23:03:40 +00:00
Dan Gohman
583938816c Now that DeadMachineInstructionElim is basically working 
correctly, it's not necessary to explicitly remove registers
from their use-def lists.

llvm-svn: 56509
 2008-09-23 22:04:18 +00:00
Dan Gohman
01a070f9c7 Arrange for FastISel code to have access to the MachineModuleInfo 
object. This will be needed to support debug info.

llvm-svn: 56508
 2008-09-23 21:53:34 +00:00
Dan Gohman
3242b7c44c Track local physical register liveness. This is not the most 
efficient implementation possible, but it's pretty simple and
good enough for the time being.

llvm-svn: 56504
 2008-09-23 21:40:44 +00:00
Dan Gohman
52a9adb3fa Replace the LiveRegs SmallSet with a simple counter that keeps 
track of the number of live registers, which is all the set was
being used for.

llvm-svn: 56498
 2008-09-23 18:50:48 +00:00
Owen Anderson
5405b59bcd Add initial support for inserting last minute copies. 
llvm-svn: 56485
 2008-09-23 04:37:10 +00:00
Dan Gohman
28970ed355 Fix the alignment of loads from constant pool entries when the 
load address has an offset from the base of the constant pool
entry.

llvm-svn: 56479
 2008-09-22 22:40:08 +00:00
Evan Cheng
0cfe303607 Livestacks really does preserve everything. 
llvm-svn: 56476
 2008-09-22 22:26:15 +00:00
Evan Cheng
1ded8b6ad6 Instead of setPreservesAll, just mark them preseving machine loop info and machine dominators. 
llvm-svn: 56475
 2008-09-22 22:21:38 +00:00
Owen Anderson
67df9bc5b8 Significant improvements to the logic for merging live intervals. This code can't 
just use LI::MergeValueAsValue, as its behavior in the presence of overlapping ranges
isn't what StrongPHIElimination wants.

llvm-svn: 56472
 2008-09-22 21:58:58 +00:00
Dale Johannesen
3722f4c14c Make log, log2, log10, exp, exp2 use Expand by 
default.

llvm-svn: 56471
 2008-09-22 21:57:32 +00:00
Evan Cheng
3bcf0cdd72 Mark several codegen passes as preserving all analysis. 
llvm-svn: 56469
 2008-09-22 20:58:04 +00:00
Dale Johannesen
375ba5ee63 More refactoring. Yawn. 
llvm-svn: 56468
 2008-09-22 20:51:30 +00:00
Dale Johannesen
a28dd108a4 Refactor FP intrinisic setup. Per review feedback. 
llvm-svn: 56456
 2008-09-22 19:51:58 +00:00
Evan Cheng
638ae1be58 Per review feedback: Only perform 
(srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
etc. when both "trunc" and "and" have single uses.

llvm-svn: 56452
 2008-09-22 18:19:24 +00:00
Oscar Fuentes
0f25988689 Initial support for the CMake build system. 
llvm-svn: 56419
 2008-09-22 01:08:49 +00:00
Bill Wendling
3ee08ff81e Add helper function to get a 32-bit floating point constant. No functionality change. 
llvm-svn: 56418
 2008-09-22 00:44:35 +00:00
Dan Gohman
98a22f8a8f Factor out code into HandleVirtRegDef, for consistency with 
Handle{Virt,Phys}Reg{Def,Use}. Remove a redundant check
for register zero, and redundant checks for isPhysicalRegister.

llvm-svn: 56412
 2008-09-21 21:11:41 +00:00
Owen Anderson
981113c401 Fetch the starting index of the block when assigning intervals. This gets live-in indices 
correct in the presence of things like EH labels.

llvm-svn: 56410
 2008-09-21 20:43:24 +00:00
Chris Lattner
01cab96cba don't print GlobalAddressSDNode's with an offset of zero as "foo0". 
llvm-svn: 56399
 2008-09-21 18:38:31 +00:00
Dale Johannesen
4a0054dc9a Teach coalescer about earlyclobber bits. 
Check bits for preferred register.

llvm-svn: 56384
 2008-09-20 02:03:04 +00:00
Evan Cheng
270178bdda Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on. 
llvm-svn: 56381
 2008-09-20 01:28:05 +00:00
Evan Cheng
23e36297d6 Continue after removing the current MI. 
llvm-svn: 56372
 2008-09-19 22:49:39 +00:00
Dan Gohman
f66b3277d3 Refactor X86SelectConstAddr, folding it into X86SelectAddress. This 
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.

llvm-svn: 56371
 2008-09-19 22:16:54 +00:00
Dale Johannesen
312df3aa6d Make earlyclobber stuff work when virtual regs 
have previously been assigned conflicting physreg.

llvm-svn: 56364
 2008-09-19 18:52:31 +00:00
Evan Cheng
14493ffe78 Re-materalized definition instructions may be dead. Whack them. 
llvm-svn: 56352
 2008-09-19 17:38:47 +00:00
Dale Johannesen
214ddc92d0 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis 
and redo as linked list walk.  Logic moved into RA.
Per review feedback.

llvm-svn: 56326
 2008-09-19 01:02:35 +00:00
Evan Cheng
bcd694a1b4 Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo. 
llvm-svn: 56314
 2008-09-18 22:38:47 +00:00
Dan Gohman
9dc56fbe40 Don't consider instructions with implicit physical register 
defs to be necessarily live.

llvm-svn: 56310
 2008-09-18 18:22:32 +00:00
Dan Gohman
b7c5b0f44b Add a new "fast" scheduler. This is currently basically just a 
copy of the BURRList scheduler, but with several parts ripped
out, such as backtracking, online topological sort maintenance
(needed by backtracking), the priority queue, and Sethi-Ullman
number computation and maintenance (needed by the priority
queue). As a result of all this, it generates somewhat lower
quality code, but that's its tradeoff for running about 30%
faster than list-burr in -fast mode in many cases.

This is somewhat experimental. Moving forward, major pieces of
this can be refactored with pieces in common with
ScheduleDAGRRList.cpp.

llvm-svn: 56307
 2008-09-18 16:26:26 +00:00
Dale Johannesen
99091ed94f Add a bit to mark operands of asm's that conflict 
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
 2008-09-17 21:13:11 +00:00
Evan Cheng
d3225118a6 Unallocatable registers do not have live intervals. 
llvm-svn: 56287
 2008-09-17 18:36:25 +00:00
Dan Gohman
4bef47e8c3 Don't worry about clobbering physical register defs that aren't used. 
llvm-svn: 56281
 2008-09-17 15:25:49 +00:00
Dan Gohman
d0c6cb65e8 Add a new MachineInstr-level DCE pass. It is very simple, and is intended to 
be used with fast-isel.

llvm-svn: 56268
 2008-09-17 00:43:24 +00:00
Evan Cheng
6cfbecd1fa When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes. 
llvm-svn: 56258
 2008-09-16 23:12:11 +00:00
Dan Gohman
9cbb3f591a Change SelectionDAG::getConstantPool to always set the alignment of the 
ConstantPoolSDNode, using the target's preferred alignment for the
constant type.

In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.

This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)

Patch by Paul Redmond!

llvm-svn: 56253
 2008-09-16 22:05:41 +00:00
Bill Wendling
932818c75a Reverting r56249. On further investigation, this functionality isn't needed. 
Apologies for the thrashing.

llvm-svn: 56251
 2008-09-16 21:48:12 +00:00
Dan Gohman
6da3227304 Include the alignment value when displaying ConstantPoolSDNodes. 
llvm-svn: 56250
 2008-09-16 21:18:22 +00:00
Bill Wendling
1a240c8033 - Change "ExternalSymbolSDNode" to "SymbolSDNode". 
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249
 2008-09-16 21:12:30 +00:00
Dan Gohman
f89b35c261 Fix these comments to reflect current reality. Surprisingly, 
MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.

llvm-svn: 56248
 2008-09-16 20:45:53 +00:00
Dan Gohman
37457ca74b Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls 
are not enabled. Instead just omit the tail call flag when calls are
created.

llvm-svn: 56235
 2008-09-16 01:42:28 +00:00
Owen Anderson
553caa6ed4 Live intervals for live-in registers should begin at the beginning of a basic block, not at the first 
instruction.  Also, their valno's should have an unknown def.  This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.

llvm-svn: 56231
 2008-09-15 22:00:38 +00:00
Dan Gohman
f38d63884f Re-enable SelectionDAG CSE for calls. It matters in the case of 
libcalls, as in this testcase on ARM.

llvm-svn: 56226
 2008-09-15 19:46:03 +00:00