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19187 Commits

Author SHA1 Message Date
David Meyer
a6e588d80c PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval 
llvm-svn: 140516
 2011-09-26 06:13:20 +00:00
Craig Topper
a08173e534 Fix VEX decoding in i386 mode. Fixes PR11008. 
llvm-svn: 140515
 2011-09-26 05:12:43 +00:00
Jakob Stoklund Olesen
7e8448c147 Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos. 
No functional change intended.

llvm-svn: 140470
 2011-09-25 16:46:08 +00:00
Akira Hatanaka
ba4a83a86b Add .td file. 
llvm-svn: 140446
 2011-09-24 01:40:18 +00:00
Akira Hatanaka
bf382ce7ed Preparation for adding simple Mips64 instructions. 
llvm-svn: 140443
 2011-09-24 01:34:44 +00:00
Jakob Stoklund Olesen
59b2982dcf Only run MF.verify() with EXPENSIVE_CHECKS=1. 
llvm-svn: 140441
 2011-09-24 01:11:19 +00:00
Owen Anderson
fc9a0d104c Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. 
llvm-svn: 140426
 2011-09-23 22:25:02 +00:00
Jakob Stoklund Olesen
ca6877343b Also match negative offsets for addrmode3 and addrmode5. 
Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

llvm-svn: 140425
 2011-09-23 22:10:33 +00:00
Owen Anderson
e63c963148 Add more fixed bits to USAT16 encoding to filter out incorrect decodings. 
llvm-svn: 140422
 2011-09-23 21:57:50 +00:00
Owen Anderson
53c6b08ad8 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
llvm-svn: 140420
 2011-09-23 21:26:40 +00:00
Owen Anderson
071eb7580a Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
llvm-svn: 140415
 2011-09-23 21:07:25 +00:00
Owen Anderson
a2cfbf33af Revert r140412. This affects more instructions than intended. 
llvm-svn: 140413
 2011-09-23 21:02:01 +00:00
Owen Anderson
227b8c74fb Thumb2 register-shifted-register loads cannot target the PC or the SP. 
llvm-svn: 140412
 2011-09-23 21:00:32 +00:00
Akira Hatanaka
224ebf0e1b Implement N32/64 calling convention. Patch by Liu. 
llvm-svn: 140401
 2011-09-23 19:08:15 +00:00
Akira Hatanaka
8573d26722 Make FGR64RegisterClass available if target is Mips64. 
llvm-svn: 140397
 2011-09-23 18:28:39 +00:00
Akira Hatanaka
1e2b0369c6 Add definitions of 64-bit register files. Add code for returning Mips64's sets of 
callee-saved registers and reserved registers.

llvm-svn: 140395
 2011-09-23 18:11:56 +00:00
Justin Holewinski
b89e54799d PTX: Fix parameter order bug 
llvm-svn: 140394
 2011-09-23 17:59:11 +00:00
Wesley Peck
aa6f35fe05 Fix a couple of 80 column violations. 
patch contributed by Jia Liu!

llvm-svn: 140391
 2011-09-23 17:24:41 +00:00
Justin Holewinski
d0190a31d3 PTX: Cleanup unused code in PTXMachineFunctionInfo 
llvm-svn: 140390
 2011-09-23 17:15:53 +00:00
Justin Holewinski
0ae669e25c PTX: Fix another 80-column violation 
llvm-svn: 140387
 2011-09-23 16:50:35 +00:00
Justin Holewinski
1c0e0dcfbe PTX: Handle function call return values 
llvm-svn: 140386
 2011-09-23 16:48:41 +00:00
Richard Osborne
0ec86a885b Fix 80 column violations. 
Original patch by Liu.

llvm-svn: 140385
 2011-09-23 16:28:10 +00:00
Duncan Sands
6d3fe8d11a Implement Chris's suggestion of legalizing the various SSE and AVX 
hadd/hsub intrinsics into the new fhadd/fhsub X86 node.

llvm-svn: 140383
 2011-09-23 16:10:22 +00:00
Justin Holewinski
0231798704 PTX: Start fixing function calls 
llvm-svn: 140378
 2011-09-23 14:31:12 +00:00
Justin Holewinski
0bb6486c58 PTX: Remove PTX calling convention files 
llvm-svn: 140377
 2011-09-23 14:18:27 +00:00
Justin Holewinski
6d69389691 [PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns 
From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
 lib/Target/PTX/PTXInstrInfo.td          |  165 ++++++++++++++++++++----------
 lib/Target/PTX/PTXIntrinsicInstrInfo.td |   88 +++++++++++------
 2 files changed, 167 insertions(+), 86 deletions(-)

llvm-svn: 140376
 2011-09-23 14:18:24 +00:00
Justin Holewinski
6353459757 PTX: Generalize handling of .param types 
llvm-svn: 140375
 2011-09-23 14:18:22 +00:00
Justin Holewinski
72d8a2bd94 PTX: Cleanup unused code in the PTXMFInfoExtract pass 
llvm-svn: 140374
 2011-09-23 14:18:19 +00:00
Akira Hatanaka
102afe6879 Add definitions of 64-bit int registers. 
llvm-svn: 140366
 2011-09-23 02:33:15 +00:00
Akira Hatanaka
f213002a1c Do not rely on the enum values of argument registers A0-A3 being consecutive. 
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.

llvm-svn: 140363
 2011-09-23 00:58:33 +00:00
Eli Friedman
31c7bde95a PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.) 
llvm-svn: 140355
 2011-09-22 23:41:28 +00:00
Akira Hatanaka
c83a0bb4b6 Make changes in instruction and pattern definitions so that tablegen does not 
complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354
 2011-09-22 23:31:54 +00:00
Jakob Stoklund Olesen
a608b612f1 Add support for GR32 <-> FR32 cross class copies. 
We already support GR64 <-> VR128 copies.  All of these copies break
partial register dependencies by zeroing the high part of the target
register.

llvm-svn: 140348
 2011-09-22 22:45:24 +00:00
Duncan Sands
1da590b589 Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from 
floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.

llvm-svn: 140332
 2011-09-22 20:15:48 +00:00
Akira Hatanaka
82aaeed7f4 Print parentheses in next line. 
llvm-svn: 140325
 2011-09-22 18:29:29 +00:00
Akira Hatanaka
7bba6afecf Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment. 
llvm-svn: 140324
 2011-09-22 18:24:21 +00:00
Akira Hatanaka
eaf1e32694 Define a new sub-register index sub_32 for accessing the 32-bit sub-register of 
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.

llvm-svn: 140319
 2011-09-22 17:57:32 +00:00
Akira Hatanaka
329b07db41 Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or 
VK_Mips_GPOFF_LO.

llvm-svn: 140316
 2011-09-22 17:44:37 +00:00
Akira Hatanaka
96122b7f72 Add F31 to the set of callee-saved registers. 
llvm-svn: 140315
 2011-09-22 17:35:03 +00:00
Akira Hatanaka
6b99d9b0f3 Fix typo. 
llvm-svn: 140313
 2011-09-22 17:26:58 +00:00
Justin Holewinski
a43c9dc50c PTX: Remove physical register defs 
llvm-svn: 140310
 2011-09-22 16:45:48 +00:00
Justin Holewinski
04f4046d9f PTX: Use .param space for device function return values on SM 2.0+, and attempt 
to fix up parameter passing on SM < 2.0

llvm-svn: 140309
 2011-09-22 16:45:46 +00:00
Justin Holewinski
987b8f7a69 PTX: Fix style issues 
llvm-svn: 140308
 2011-09-22 16:45:43 +00:00
Justin Holewinski
815227205d PTX: Fixup codegen to handle emission of virtual registers. 
llvm-svn: 140307
 2011-09-22 16:45:40 +00:00
Justin Holewinski
1dd4cf37f8 PTX: Customize codegen passes in backend 
llvm-svn: 140306
 2011-09-22 16:45:37 +00:00
Justin Holewinski
fee8e64e4d PTX: Add new PTX-specific register allocator that keeps virtual registers 
instead of allocating physical registers.

This is part of a work-in-progress overhaul of the PTX register allocation scheme.

llvm-svn: 140305
 2011-09-22 16:45:33 +00:00
Craig Topper
95f048d1ff Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 
llvm-svn: 140299
 2011-09-22 07:01:50 +00:00
Akira Hatanaka
12218a1192 Add definition of 64-bit floating registers used for Mips64. 
llvm-svn: 140297
 2011-09-22 03:48:47 +00:00
Benjamin Kramer
978ef840ac The SSE version differences for fmin/fmax are more involved than I thought. 
- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)

llvm-svn: 140296
 2011-09-22 03:27:22 +00:00
Akira Hatanaka
d34925f313 Add enums and functions for symbols Mips64 uses. 
llvm-svn: 140295
 2011-09-22 03:09:07 +00:00