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20266 Commits

Author SHA1 Message Date
Jim Grosbach
90f8398ee6 ARM assembly parser canonicallize on 'lsl' for shift-by-zero form. 
llvm-svn: 147152
 2011-12-22 17:37:00 +00:00
Jim Grosbach
8ca95cbf58 Tidy up. Trailing whitespace. 
llvm-svn: 147151
 2011-12-22 17:17:10 +00:00
Jim Grosbach
65cd6c7acc Nuke invalid comment from copy/paste. 
llvm-svn: 147150
 2011-12-22 17:04:50 +00:00
Rafael Espindola
3ed0f04e50 Move the Mips only bits of the ELF writer to lib/Target/Mips. 
llvm-svn: 147133
 2011-12-22 03:03:17 +00:00
Rafael Espindola
57dea1bf84 Make the virtual methods in ARMELFObjectWriter public. 
llvm-svn: 147132
 2011-12-22 02:58:12 +00:00
Rafael Espindola
82d61c8b38 Move the MBlaze ELF writer bits to lib/Target/MBlaze. 
llvm-svn: 147129
 2011-12-22 02:28:24 +00:00
Rafael Espindola
b3756d8e4d Fix cmake. 
llvm-svn: 147126
 2011-12-22 02:06:17 +00:00
Rafael Espindola
9c71db357e Move PPC bits to lib/Target/PowerPC. 
llvm-svn: 147124
 2011-12-22 01:57:09 +00:00
Rafael Espindola
6f3a1698f3 Hopefully fix the cmake build. 
llvm-svn: 147121
 2011-12-22 01:11:01 +00:00
Rafael Espindola
6f21886d7e Fix name in comments. 
llvm-svn: 147119
 2011-12-22 01:06:53 +00:00
Akira Hatanaka
e7bcf63d98 Local dynamic TLS model for direct object output. Create the correct TLS MIPS 
ELF relocations.

Patch by Jack Carter.

llvm-svn: 147118
 2011-12-22 01:05:17 +00:00
Richard Smith
9b355262f5 Unbreak cmake build after r147115. 
llvm-svn: 147117
 2011-12-22 01:03:35 +00:00
Rafael Espindola
ee837037ee Move the ARM specific parts of the ELF writer to Target/ARM. 
llvm-svn: 147115
 2011-12-22 00:37:50 +00:00
Jim Grosbach
1b11b334a4 ARM NEON mnemonic aliase for vrecpeq. 
llvm-svn: 147109
 2011-12-21 23:52:37 +00:00
Jim Grosbach
7d31680e2d ARM VFP optional data type on VMOV GPR<-->SPR. 
llvm-svn: 147104
 2011-12-21 23:24:15 +00:00
Jim Grosbach
35b5afad26 ARM NEON optional data type on VSWP instructions. 
llvm-svn: 147103
 2011-12-21 23:09:28 +00:00
Jim Grosbach
64df852f5b ARM NEON mnemonic aliases for vzipq and vswpq. 
llvm-svn: 147102
 2011-12-21 23:04:33 +00:00
Jim Grosbach
88eacffd72 ARM asm parser should be more lenient w/ .thumb_func directive. 
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

llvm-svn: 147100
 2011-12-21 22:30:16 +00:00
Jim Grosbach
2bbc41fa26 Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

llvm-svn: 147096
 2011-12-21 21:04:19 +00:00
Chad Rosier
98251404f7 Fix 80-column violations. 
llvm-svn: 147095
 2011-12-21 20:59:09 +00:00
Jim Grosbach
91faf5d15f Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

llvm-svn: 147094
 2011-12-21 20:54:00 +00:00
Jakob Stoklund Olesen
893037ce23 Move common code into an MRI function. 
llvm-svn: 147071
 2011-12-21 19:50:05 +00:00
Jim Grosbach
f7236d1084 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
llvm-svn: 147069
 2011-12-21 19:40:55 +00:00
Chad Rosier
4e4bfcaa90 No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't 
necessary.  Please chime in if I'm mistaken.

llvm-svn: 147065
 2011-12-21 19:14:52 +00:00
Chad Rosier
c2f31859cc Fix a couple of copy-n-paste bugs. Noticed by George Russell! 
llvm-svn: 147064
 2011-12-21 18:56:22 +00:00
Rafael Espindola
8c9b0dea02 Move the X86 specific bits of the ELF writer to the Target/X86 directory. 
Other targets will follow shortly.

llvm-svn: 147060
 2011-12-21 17:30:17 +00:00
Rafael Espindola
f9c7f9e3f3 Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059
 2011-12-21 17:00:36 +00:00
Craig Topper
496932a88a Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. 
llvm-svn: 147046
 2011-12-21 08:06:52 +00:00
Craig Topper
e2e670bee5 Fix typo in a couple comments 
llvm-svn: 147045
 2011-12-21 06:30:53 +00:00
Evan Cheng
fb22f64814 Fix a couple of copy-n-paste bugs. Noticed by George Russell. 
llvm-svn: 147032
 2011-12-21 03:04:10 +00:00
Jim Grosbach
2c2140a128 ARM assembly parsing allows constant expressions for lane indices. 
llvm-svn: 147028
 2011-12-21 01:19:23 +00:00
Jim Grosbach
6bd1044b03 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
llvm-svn: 147025
 2011-12-21 00:38:54 +00:00
Akira Hatanaka
4ab17eaca0 Fix bug in zero-store peephole pattern reported in pr11615. 
The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024
 2011-12-21 00:31:10 +00:00
Akira Hatanaka
0af792d12b Expand 64-bit CTLZ nodes if target architecture does not support it. Add test 
case for DCLO and DCLZ.

llvm-svn: 147022
 2011-12-21 00:20:27 +00:00
Akira Hatanaka
6454b0ffc1 Expand 64-bit CTPOP and CTTZ. 
llvm-svn: 147021
 2011-12-21 00:14:05 +00:00
Akira Hatanaka
0cc0498ea1 Expand 64-bit atomic load and store. 
llvm-svn: 147019
 2011-12-21 00:02:58 +00:00
Akira Hatanaka
2d293d2f4c Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
 2011-12-20 23:56:43 +00:00
Akira Hatanaka
fa96454cb4 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015
 2011-12-20 23:47:44 +00:00
Akira Hatanaka
6f31d220e7 64-bit uint-fp conversion nodes are expanded. 
llvm-svn: 147014
 2011-12-20 23:40:56 +00:00
Akira Hatanaka
02fe8adb97 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
llvm-svn: 147013
 2011-12-20 23:35:46 +00:00
Akira Hatanaka
507cdacdde Set the correct stack pointer register that should be saved or restored. 
llvm-svn: 147012
 2011-12-20 23:28:36 +00:00
Jim Grosbach
7baaa0fc64 ARM .req register name aliases are case insensitive, just like regnames. 
llvm-svn: 147009
 2011-12-20 23:11:00 +00:00
Akira Hatanaka
2e4f1786b1 Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates 
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008
 2011-12-20 23:10:57 +00:00
Akira Hatanaka
8e3e6b14c8 Fix indentation. 
llvm-svn: 147007
 2011-12-20 22:58:01 +00:00
Akira Hatanaka
f728a1b2c5 64-bit data directive. 
llvm-svn: 147005
 2011-12-20 22:52:19 +00:00
Akira Hatanaka
ad193d95ae 32-to-64-bit sext_inreg pattern. 
llvm-svn: 147004
 2011-12-20 22:40:40 +00:00
Akira Hatanaka
13f23f5895 Add 64-bit extload patterns. 
llvm-svn: 147003
 2011-12-20 22:36:08 +00:00
Akira Hatanaka
ed1a29d5c2 Add patterns for matching extloads with 64-bit address. The patterns are enabled 
only when the target ABI is N64.

llvm-svn: 147001
 2011-12-20 22:33:53 +00:00
Jim Grosbach
ff31b81fe2 Move comment to appropriate place. 
llvm-svn: 147000
 2011-12-20 22:26:38 +00:00
Akira Hatanaka
8728f4ed69 Add code in MipsDAGToDAGISel for selecting constant +0.0. 
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999
 2011-12-20 22:25:50 +00:00