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Commit Graph

7477 Commits

Author SHA1 Message Date
Rafael Espindola
9182560b8f Fix comment. Noticed by Duncan.
llvm-svn: 139161
2011-09-06 19:29:31 +00:00
Duncan Sands
d1311488fe Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
2011-09-06 19:07:46 +00:00
Rafael Espindola
9d9df4bc1a Fix style issues and typos found by Duncan.
llvm-svn: 139154
2011-09-06 18:43:08 +00:00
Duncan Sands
6939ae53ac Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

llvm-svn: 139140
2011-09-06 13:37:06 +00:00
Nick Lewycky
9b5a242546 Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!

llvm-svn: 139125
2011-09-05 21:51:43 +00:00
Benjamin Kramer
902004dcd8 Use internal storage for command line option.
llvm-svn: 139079
2011-09-03 03:45:06 +00:00
Bruno Cardoso Lopes
02157d584a Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends
the cycle of missing AVX counterparts of already present SSE* patterns

llvm-svn: 139073
2011-09-03 00:47:08 +00:00
Bruno Cardoso Lopes
c72ce24240 Add AVX version of a SSE4.1 VPBLENDVB pattern
llvm-svn: 139072
2011-09-03 00:47:05 +00:00
Bruno Cardoso Lopes
a25fc6f941 Add AVX versions of SSE4.1 EXTRACTPS patterns
llvm-svn: 139071
2011-09-03 00:47:03 +00:00
Bruno Cardoso Lopes
45d02d5eca Add AVX versions for SSE4.1 MOVZX* patterns
llvm-svn: 139070
2011-09-03 00:47:01 +00:00
Bruno Cardoso Lopes
cadec3711c Add one more AVX pattern for MOVZPQILo2PQI
llvm-svn: 139069
2011-09-03 00:46:58 +00:00
Bruno Cardoso Lopes
48eeb79003 Move PUNPCKLQDQ splat pattern close to the instruction definition and
duplicate it for AVX mode.

llvm-svn: 139068
2011-09-03 00:46:56 +00:00
Bruno Cardoso Lopes
ca90af60bd Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
llvm-svn: 139067
2011-09-03 00:46:54 +00:00
Bruno Cardoso Lopes
7fae5ca308 Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate
that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.

llvm-svn: 139066
2011-09-03 00:46:51 +00:00
Bruno Cardoso Lopes
e749426ece Enforce subtarget checks in a few places to be explicit when the
pattern should be matched

llvm-svn: 139065
2011-09-03 00:46:49 +00:00
Bruno Cardoso Lopes
323a5b334e Tidy up code moving patterns to their appropriate place!
llvm-svn: 139064
2011-09-03 00:46:47 +00:00
Bruno Cardoso Lopes
ea1931b9d0 Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use
it!

llvm-svn: 139063
2011-09-03 00:46:45 +00:00
Bruno Cardoso Lopes
eb041875c1 Teach X86FastISel to use AVX versions of instructions when possible
llvm-svn: 139062
2011-09-03 00:46:42 +00:00
Bruno Cardoso Lopes
86c67e11c9 Fix 80-column and style
llvm-svn: 139061
2011-09-03 00:46:40 +00:00
Bruno Cardoso Lopes
beb7a448e7 Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of
OptForSize pattern

llvm-svn: 139060
2011-09-03 00:46:38 +00:00
Jakob Stoklund Olesen
ef8527b836 Pseudo CMOV instructions don't clobber EFLAGS.
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057
2011-09-02 23:52:55 +00:00
Jakob Stoklund Olesen
29145a3de1 Check for EFLAGS live-out before clobbering it.
It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.

llvm-svn: 139056
2011-09-02 23:52:52 +00:00
Jakob Stoklund Olesen
6d5d51f687 Use existing function.
llvm-svn: 139055
2011-09-02 23:52:49 +00:00
Jakob Stoklund Olesen
c710d8fdc7 Remove unused variables.
llvm-svn: 139047
2011-09-02 22:41:25 +00:00
Eli Friedman
383a3c76b2 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
Kevin Enderby
90a1526592 Change X86 disassembly to print immediates values as signed by default. Special
case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028
2011-09-02 20:01:23 +00:00
Bill Wendling
991a1dab16 Revert r138826 until PR10834 can be fixed.
llvm-svn: 139018
2011-09-02 18:15:04 +00:00
Bruno Cardoso Lopes
10f234f1a7 Fix vbroadcast matching logic to early unmatch if the node doesn't have
only one use. Fix PR10825.

llvm-svn: 138951
2011-09-01 18:15:06 +00:00
Bruno Cardoso Lopes
8771512b75 Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS
llvm-svn: 138897
2011-08-31 21:15:32 +00:00
Bruno Cardoso Lopes
22aceefbf7 Move MOVAPS,MOVUPS patterns close to the instructions definition
llvm-svn: 138896
2011-08-31 21:15:29 +00:00
Bruno Cardoso Lopes
4823fe07e6 Remove "_Int" forms of MOVUPSmr and MOVAPSmr
llvm-svn: 138895
2011-08-31 21:15:22 +00:00
Rafael Espindola
295e404961 Spelling and grammar fixes to problems found by Duncan.
llvm-svn: 138858
2011-08-31 16:43:33 +00:00
Eli Friedman
4fefb0a561 Make sure we don't crash when -miphoneos-version-min is specified on x86. Hopefully this will fix gcc testsuite failures.
llvm-svn: 138856
2011-08-31 16:19:51 +00:00
Eric Christopher
157bf8b08d Rework this conditional a bit.
Patch by Sanjoy Das

llvm-svn: 138853
2011-08-31 04:17:21 +00:00
Bruno Cardoso Lopes
5bd6e92f99 - Move all MOVSS and MOVSD patterns close to their definitions
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

llvm-svn: 138851
2011-08-31 03:04:20 +00:00
Bruno Cardoso Lopes
a9c2c56e13 Remove unnecessary AVX checks
llvm-svn: 138850
2011-08-31 03:04:14 +00:00
Bruno Cardoso Lopes
fe3f3344a6 Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS,
whenever AVX is enabled.

llvm-svn: 138849
2011-08-31 03:04:09 +00:00
Evan Cheng
bbabe9ff60 Fix (movhps load) lowering / pattern to match more cases. rdar://10050549
llvm-svn: 138848
2011-08-31 02:05:24 +00:00
Bill Wendling
1e8c335302 Fix off-by-one error Benjamin noticed.
llvm-svn: 138832
2011-08-30 21:23:24 +00:00
Bill Wendling
569b9fee87 Enable compact unwind info by default. This only applies to Darwin when CFI is
disabled.

llvm-svn: 138826
2011-08-30 20:54:11 +00:00
Jeffrey Yasskin
8f36e758c2 Fix C++0x narrowing errors when char is unsigned.
In the case of EDInstInfo, this would actually cause a bug when -1 became 255
and was then compared >=0 in llvm-mc/Disassembler.cpp.

llvm-svn: 138825
2011-08-30 20:53:29 +00:00
Rafael Espindola
9db302e741 Adds support for variable sized allocas. For a variable sized alloca,
code is inserted to first check if the current stacklet has enough
space. If so, space is allocated by simply decrementing the stack
pointer. Otherwise a runtime routine (__morestack_allocate_stack_space
in libgcc) is called which allocates the required memory from the
heap.

Patch by Sanjoy Das.

llvm-svn: 138818
2011-08-30 19:47:04 +00:00
Rafael Espindola
7721c15106 Adds a SelectionDAG node X86SegAlloca which will be custom lowered
from DYNAMIC_STACKALLOC.

Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added.  They
will be custom emitted to inject the actual stack handling code.

Patch by Sanjoy Das.

llvm-svn: 138814
2011-08-30 19:43:21 +00:00
Rafael Espindola
321e47cd0b Emit segmented-stack specific code into function prologues for
X86. Modify the pass added in the previous patch to call this new
code.

This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required

Patch by Sanjoy Das.

llvm-svn: 138812
2011-08-30 19:39:58 +00:00
Eli Friedman
4d90e53381 Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802.
llvm-svn: 138768
2011-08-29 21:15:46 +00:00
Bruno Cardoso Lopes
3a09888a72 Move non-intruction patterns to a more appropriate place!
llvm-svn: 138744
2011-08-29 17:51:24 +00:00
Nicolas Geoffray
74b006fe71 Remove premature previous commit.
llvm-svn: 138725
2011-08-28 14:52:51 +00:00
Nicolas Geoffray
d30e51ca07 Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does.
llvm-svn: 138723
2011-08-28 13:07:57 +00:00
Benjamin Kramer
6411b8f81a Silence GCC warnings and make an array const.
llvm-svn: 138706
2011-08-27 17:36:14 +00:00
Eli Friedman
9f95c7d381 Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
llvm-svn: 138660
2011-08-26 21:21:21 +00:00