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Commit Graph

36 Commits

Author SHA1 Message Date
Bob Wilson
92bf5a7425 Add a Thumb2 t2RSBrr instruction for disassembly only.
This fixes another part of PR7792.

llvm-svn: 111057
2010-08-13 23:24:25 +00:00
Bob Wilson
0883c6aae3 Move the Thumb2 SSAT and USAT optional shift operator out of the
instruction opcode.  This fixes part of PR7792.

llvm-svn: 111047
2010-08-13 21:48:10 +00:00
Johnny Chen
78345b1dfe Cleaned up the for-disassembly-only entries in the arm instruction table so that
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951
2010-08-12 20:46:17 +00:00
Johnny Chen
fef1367b50 The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894
2010-08-12 01:40:54 +00:00
Johnny Chen
9a37d16281 Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
Added two test cases to arm-tests.txt.

llvm-svn: 110880
2010-08-11 23:35:12 +00:00
Bob Wilson
3582107cf8 Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
2010-08-11 23:10:46 +00:00
Bob Wilson
4ba3c0a5e1 Add an ARM RSCrr instruction for disassembly only.
Partial fix for PR7792.

llvm-svn: 110361
2010-08-05 18:59:36 +00:00
Bob Wilson
9fbaea3765 Add an ARM RSBrr instruction for disassembly only.
Partial fix for PR7792.

llvm-svn: 110358
2010-08-05 18:23:43 +00:00
Bob Wilson
214b004717 ARM "rrx" shift operands do not have an immediate. PR7790.
llvm-svn: 110292
2010-08-05 00:34:42 +00:00
Bob Wilson
439e7b1d73 Add support for disassembling VMVN (immediate) instructions. PR7747.
llvm-svn: 109946
2010-07-31 05:57:44 +00:00
Chris Lattner
ddb09ea6ad my work on adding segment registers to LEA missed the
disassembler.  Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.

llvm-svn: 108226
2010-07-13 04:23:55 +00:00
Sean Callanan
4331428e24 Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196
2010-05-06 20:59:00 +00:00
Johnny Chen
6e4b1607ee Thumb instructions which have reglist operands at the end and predicate operands
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.

llvm-svn: 101974
2010-04-21 01:01:19 +00:00
Johnny Chen
9998480f92 When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.

llvm-svn: 101929
2010-04-20 18:45:24 +00:00
Johnny Chen
bd5bf58029 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915
2010-04-20 17:28:50 +00:00
Johnny Chen
fe24cdbba8 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.

llvm-svn: 101817
2010-04-19 21:19:52 +00:00
Johnny Chen
091c01cb2f ARM disassembler did not react to recent changes to the NEON instruction table.
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.

llvm-svn: 101784
2010-04-19 16:20:34 +00:00
Chris Lattner
80a22bfcdb testcase for r101538, patch by Nico Schmidt!
llvm-svn: 101642
2010-04-17 17:22:06 +00:00
Johnny Chen
1b78f89844 Minor change to make the test case comply with Vd<0> == '0' when Q == '1'.
llvm-svn: 101559
2010-04-16 22:48:31 +00:00
Johnny Chen
44087236da Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().

llvm-svn: 101557
2010-04-16 22:40:20 +00:00
Johnny Chen
7ac96eac03 In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.

llvm-svn: 101529
2010-04-16 19:57:21 +00:00
Johnny Chen
3cc0200f74 Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().

llvm-svn: 101527
2010-04-16 19:33:23 +00:00
Johnny Chen
0017916a36 Added another test case for am3offset operand, testing Rn, #+/-imm8.
Previous checkin tested Rn, #+/-Rm.

llvm-svn: 101418
2010-04-15 23:23:40 +00:00
Johnny Chen
53225c4582 Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
am2offset.  Modified the instruction table entry and added a new test case.

llvm-svn: 101415
2010-04-15 23:12:47 +00:00
Daniel Dunbar
cc40ce33de tests: MC/Disassembler tests depend on ARM support being compiler in.
llvm-svn: 101337
2010-04-15 03:47:20 +00:00
Johnny Chen
7a729daf31 Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2.
Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from
ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V).

[12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc
GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB.  Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done

(gdb) set args  -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
(gdb) r
Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
Reading symbols for shared libraries ++. done
0xf5 0x71 0xf0 0x53
Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1|
-------------------------------------------------------------------------------------------------

	mvnpls	r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229.

Program received signal SIGABRT, Aborted.
0x00007fff88c65886 in __kill ()
(gdb) bt
#0  0x00007fff88c65886 in __kill ()
#1  0x00007fff88d05eae in abort ()
#2  0x00007fff88cf2ef0 in __assert_rtn ()
#3  0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229
#4  0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254
#5  0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236
#6  0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182
#7  0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65
#8  0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153
#9  0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347
#10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374
(gdb) q
The program is running.  Exit anyway? (y or n) y
[13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ 

llvm-svn: 101053
2010-04-12 18:46:53 +00:00
Benjamin Kramer
0230783438 unXFAIL, arm disassembler was reenabled.
llvm-svn: 100692
2010-04-07 21:19:41 +00:00
Evan Cheng
dbf0c22d5b Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests.
llvm-svn: 100378
2010-04-05 01:04:27 +00:00
Johnny Chen
6d9cbe7270 Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.

llvm-svn: 100233
2010-04-02 22:27:38 +00:00
Kevin Enderby
23e37f3e39 Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytes
for the encoding and is not the same as vmptrld.

llvm-svn: 97992
2010-03-08 22:17:26 +00:00
Chris Lattner
8530ba626c add encoder support and tests for rdtscp
llvm-svn: 96076
2010-02-13 03:42:24 +00:00
Chris Lattner
5b01ab848c remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
fix swapgs to be spelled right.

llvm-svn: 96058
2010-02-13 00:41:14 +00:00
Chris Lattner
c80a6de0a9 add some disassemble testcases for weird instructions
llvm-svn: 96045
2010-02-12 23:46:48 +00:00
Chris Lattner
de6faded57 specify a triple to use, fixing the test on non-x86-64 hosts.
llvm-svn: 91900
2009-12-22 07:01:12 +00:00
Chris Lattner
226e849772 various cleanups, make the disassemble reject lines with too much
data on them, for example:

	addb	%al, (%rax)
simple-tests.txt:11:5: error: excess data detected in input
0 0 0 0 0 
    ^

llvm-svn: 91896
2009-12-22 06:56:51 +00:00
Chris Lattner
3b333ebfb8 rewrite the file parser for the disassembler, implementing support for
comments.  Also, check in a simple testcase for the disassembler,
including a test for r91864

llvm-svn: 91894
2009-12-22 06:37:58 +00:00