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Commit Graph

197654 Commits

Author SHA1 Message Date
Matt Arsenault
0ba1ec26dd DAG: Fix getNode dropping flags if there's a glue output
The AMDGPU non-strict fdiv lowering needs to introduce an FP mode
switch in some cases, and has custom nodes to provide chain/glue for
the intermediate FP operations. We need to propagate nofpexcept here,
but getNode was dropping the flags.

Adding nofpexcept in the AMDGPU custom lowering is left to a future
patch.

Also fix a second case where flags were dropped, but in this case it
seems it just didn't handle this number of operands.

Test will be included in future AMDGPU patch.
2020-06-01 13:48:02 -04:00
Hiroshi Yamauchi
c65f25e192 [PGO] Improve the working set size heuristics under the partial sample PGO.
Summary:
The working set size heuristics (ProfileSummaryInfo::hasHugeWorkingSetSize)
under the partial sample PGO may not be accurate because the profile is partial
and the number of hot profile counters in the ProfileSummary may not reflect the
actual working set size of the program being compiled.

To improve this, the (approximated) ratio of the the number of profile counters
of the program being compiled to the number of profile counters in the partial
sample profile is computed (which is called the partial profile ratio) and the
working set size of the profile is scaled by this ratio to reflect the working
set size of the program being compiled and used for the working set size
heuristics.

The partial profile ratio is approximated based on the number of the basic
blocks in the program and the NumCounts field in the ProfileSummary and computed
through the thin LTO indexing. This means that there is the limitation that the
scaled working set size is available to the thin LTO post link passes only.

Reviewers: davidxl

Subscribers: mgorny, eraman, hiraditya, steven_wu, dexonsmith, arphaman, dang, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79831
2020-06-01 10:29:23 -07:00
Matt Arsenault
3fc69c930e AMDGPU: Fix test in code directory 2020-06-01 13:26:51 -04:00
Matt Arsenault
bf7398d4cf AMDGPU: Remove dead file 2020-06-01 13:26:51 -04:00
hsmahesha
ed5decd2c8 [AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
Summary:
While clustering mem ops, AMDGPU target needs to consider number of clustered bytes
to decide on max number of mem ops that can be clustered. This patch adds support to pass
number of clustered bytes to target mem ops clustering logic.

Reviewers: foad, rampitec, arsenm, vpykhtin, javedabsar

Reviewed By: foad

Subscribers: MatzeB, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, javed.absar, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80545
2020-06-01 22:52:34 +05:30
Stanislav Mekhanoshin
d47b2c2a4b Temporarily removed unstable test. NFC. 2020-06-01 10:18:54 -07:00
Matt Arsenault
7e6b33626b AMDGPU: Fix alignment for dynamic allocas
The alignment value also needs to be scaled by the wave size.
2020-06-01 13:06:37 -04:00
Stanislav Mekhanoshin
3f75cfd780 Update some names in test. NFC.
There seems to be some instability with IR nameing between
platforms. Attempted to fix it with replacing dot-numbered
names.
2020-06-01 09:11:18 -07:00
Fangrui Song
18064a73bd [Object] Add DF_1_PIE
This flag (and the whole field DT_FLAGS_1) originated from Solaris. I intend to use it in an LLD patch D80872.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D80871
2020-06-01 08:56:02 -07:00
Sanjay Patel
8cc0da7038 [InstCombine] add test for select-of-shuffle; NFC
This is based on an example in D80658
2020-06-01 11:52:07 -04:00
Stanislav Mekhanoshin
17a709861f Process gep (phi ptr1, ptr2) in SROA
Differential Revision: https://reviews.llvm.org/D79218
2020-06-01 08:41:05 -07:00
Sam Clegg
232d118233 [WebAssembly] Update test expectations
simd-2.C now compiles thanks to:
  https://github.com/WebAssembly/wasi-libc/pull/183

Differential Revision: https://reviews.llvm.org/D80930
2020-06-01 08:35:27 -07:00
Sanjay Patel
24f9324c29 [InstNamer] use 'i' for Instructions, not 'tmp'
As discussed in https://bugs.llvm.org/show_bug.cgi?id=45951 and
D80584, the name 'tmp' is almost always a bad choice, but we have
a legacy of regression tests with that name because it was baked
into utils/update_test_checks.py.

This change makes -instnamer more consistent (already using "arg"
and "bb", the common LLVM shorthand). And it avoids the conflict
in telling users of the FileCheck script to run "-instnamer" to
create a better regression test and having that cause a warn/fail
in update_test_checks.py.
2020-06-01 11:11:14 -04:00
Ehud Katz
1b0a29266b [StructurizeCFG] Fix an incorrect comment, NFC. 2020-06-01 17:42:09 +03:00
James Henderson
47c0f73fb2 [Support] Add more context to DataExtractor getLEB128 errors
Reviewed by: clayborg, dblaikie, labath

Differential Revision: https://reviews.llvm.org/D80799
2020-06-01 14:00:01 +01:00
James Henderson
b5cd4f0921 [DebugInfo] Add use of truncating data extractor to debug line parsing
This will ensure that nothing can ever start parsing data from a future
sequence and part-read data will be returned as 0 instead.

Reviewed by: aprantl, labath

Differential Revision: https://reviews.llvm.org/D80796
2020-06-01 12:33:21 +01:00
Sanjay Patel
804d4bd875 [utils] change default nameless value to "TMP"
This is effectively reverting rGbfdc2552664d to avoid test churn
while we figure out a better way forward.

We at least salvage the warning on name conflict from that patch
though.

If we change the default string again, we may want to mass update
tests at the same time. Alternatively, we could live with the poor
naming if we change -instnamer.

This also adds a test to LLVM as suggested in the post-commit
review. There's a clang test that is also affected. That seems
like a layering violation, but I have not looked at fixing that yet.

Differential Revision: https://reviews.llvm.org/D80584
2020-06-01 06:54:45 -04:00
James Henderson
129a1ceed7 [llvm-dwarfdump][test] Use verbose output to check expected opcodes
The debug_line_invalid.test test case was previously using the
interpreted line table dumping to identify which opcodes have been
parsed. This change moves to looking for the expected opcodes
explicitly. This is probably a little clearer and also allows for
testing some cases that wouldn't be easily identifiable from the
interpreted table.

Reviewed by: MaskRay

Differential Revision: https://reviews.llvm.org/D80795
2020-06-01 11:48:02 +01:00
Simon Pilgrim
61aa867bc8 ARMFrameLowering.h - remove unnecessary includes. NFC.
They are implicitly included in TargetFrameLowering.h and only ever used in TargetFrameLowering override methods.
2020-06-01 11:47:13 +01:00
Simon Pilgrim
b88b305492 MIPatternMatch.h - remove unused APFloat/APInt includes. NFC. 2020-06-01 11:47:13 +01:00
Igor Kudrin
515faba258 [DebugInfo] Separate fields with commas in headers of type units (3/3).
For most tables, we already use commas in headers. This set of patches
unifies dumping the remaining ones.

Differential Revision: https://reviews.llvm.org/D80806
2020-06-01 17:40:28 +07:00
Igor Kudrin
b9c53c8d85 [DebugInfo] Separate fields with commas in headers of compile units (2/3).
For most tables, we already use commas in headers. This set of patches
unifies dumping the remaining ones.

Differential Revision: https://reviews.llvm.org/D80806
2020-06-01 17:40:24 +07:00
Igor Kudrin
e1c94df8e4 [DebugInfo] Separate fields with commas in headers of .debug_pub* tables (1/3).
For most tables, we already use commas in headers. This set of patches
unifies dumping the remaining ones.

Differential Revision: https://reviews.llvm.org/D80806
2020-06-01 17:39:48 +07:00
Georgii Rymar
516ffefcde [llvm-readelf] - Add explicit braces again. NFC.
Partially reverts feee98645dde4be31a70cc6660d2fc4d4b9d32d8.

Add explicit braces to a different place to fix
"error: add explicit braces to avoid dangling else [-Werror,-Wdangling-else]"
2020-06-01 13:10:16 +03:00
Georgii Rymar
c01c172f33 [llvm-readelf] - Add explicit braces. NFC.
Should fix the BB (http://lab.llvm.org:8011/builders/clang-ppc64le-rhel/builds/3907/steps/build%20stage%201/logs/stdio):

llvm-readobj/ELFDumper.cpp:4708:5: error: add explicit braces to avoid dangling else [-Werror,-Wdangling-else]
    else
    ^
2020-06-01 12:55:24 +03:00
Ehud Katz
9df1915a6d [StructurizeCFG] Fix region nodes ordering
This is a reimplementation of the `orderNodes` function, as the old
implementation didn't take into account all cases.
The new implementation uses SCCs instead of Loops to take account of
irreducible loops.

Fix PR41509

Differential Revision: https://reviews.llvm.org/D79037
2020-06-01 12:50:35 +03:00
Georgii Rymar
ac85d75310 [llvm-readobj] - Improve error reporting for hash tables.
This improves the next points for broken hash tables:

1) Use reportUniqueWarning to prevent duplication when
   --hash-table and --elf-hash-histogram are used together.

2) Dump nbuckets and nchain fields. It is often possible
   to dump them even when the table itself goes past the EOF etc.

Differential revision: https://reviews.llvm.org/D80373
2020-06-01 12:36:23 +03:00
Tim Northover
8b6ab03c03 AArch64: materialize large stack offset into xzr correctly.
When a stack offset was too big to materialize in a single instruction, we were
trying to do it in stages:

    adds xD, sp, #imm
    adds xD, xD, #imm

Unfortunately, if xD is xzr then the second instruction doesn't exist and
wouldn't do what was needed if it did. Instead we can use a temporary register
for all but the last addition.
2020-06-01 09:30:05 +01:00
serge-sans-paille
ffa794c4cb Improve SmallPtrSetImpl::count implementation
Relying on the find method implies a roundtrip to the iterator world, which is
not costless because iterator creation involves a few check to ensure the
iterator is in a valid position (through the SmallPtrSetIteratorImpl::AdvanceIfNotValid
method). It turns out that the result of SmallPtrSetImpl::find_imp is either
valid or the EndPointer, so there's no need to go through that abstraction,
and the compiler cannot guess it.

Differential Revision: https://reviews.llvm.org/D80708
2020-06-01 07:49:19 +02:00
Chen Zheng
c5c4a9bca7 [MachineCombine] add a hook for resource length limit 2020-05-31 23:21:04 -04:00
Li Rong Yi
80a001669f [PowerPC] Exploit vabsd on P9
Summary: Exploit vabsd* for for absolute difference of vectors on P9,
for example:
void foo (char *restrict p, char *restrict q, char *restrict t)
{
  for (int i = 0; i < 16; i++)
     t[i] = abs (p[i] - q[i]);
}
this case should be matched to the HW instruction vabsdub.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D80271
2020-06-01 02:30:27 +00:00
Nico Weber
6f003d58d9 [gn build] (semi-manually) port a8ca0ec2670 2020-05-31 22:06:11 -04:00
Matt Arsenault
ab446506d6 AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass 2020-05-31 20:40:14 -04:00
Craig Topper
12253f5671 [X86] Rewrite how X86PartialReduction finds candidates to consider optimizing.
Previously we walked the users of any vector binop looking for
more binops with the same opcode or phis that eventually ended up
in a reduction. While this is simple it also means visiting the
same nodes many times since we'll do a forward walk for each
BinaryOperator in the chain. It was also far more general than what
we have tests for or expect to see.

This patch replaces the algorithm with a new method that starts at
extract elements looking for a horizontal reduction. Once we find
a reduction we walk through backwards through phis and adds to
collect leaves that we can consider for rewriting.

We only consider single use adds and phis. Except for a special
case if the Add is used by a phi that forms a loop back to the
Add. Including other single use Adds to support unrolled loops.

Ultimately, I want to narrow the Adds, Phis, and final reduction
based on the partial reduction we're doing. I still haven't
figured out exactly what that looks like yet. But restricting
the types of graphs we expect to handle seemed like a good first
step. As does having all the leaves and the reduction at once.

Differential Revision: https://reviews.llvm.org/D79971
2020-05-31 12:53:01 -07:00
Simon Pilgrim
885928e3e6 [X86][AVX] Reduce unary target shuffles width if the upper elements aren't demanded. 2020-05-31 20:19:24 +01:00
Simon Pilgrim
9e57ca5e0e [X86][AVX] combineX86ShufflesRecursively - peekThroughOneUseBitcasts subvector before widening.
This matches what we do for the full sized vector ops at the start of combineX86ShufflesRecursively, and helps getFauxShuffleMask extract more INSERT_SUBVECTOR patterns.
2020-05-31 19:58:33 +01:00
Matt Arsenault
354a94569e AArch64/GlobalISel: Fix incorrect ptrmask usage for alignment
I inverted the mask when I ported to the new form of G_PTRMASK in
8bc03d2168241f7b12265e9cd7e4eb7655709f34.

I don't think this really broke anything, since G_VASTART isn't
handled for types with an alignment higher than the stack alignment.
2020-05-31 10:56:55 -04:00
Sanjay Patel
2ca9a76699 [utils] change update_test_checks.py use of 'TMP' value names
As discussed in PR45951:
https://bugs.llvm.org/show_bug.cgi?id=45951

There's a potential name collision between update_test_checks.py and -instnamer
and/or manually-generated IR test files because all of them try to use the
variable name that should never be used: "tmp".

This patch proposes to reduce the odds of collision and adds a warning if we
detect the problem. This will cause regression test churn when regenerating
CHECK lines on existing files.

Differential Revision: https://reviews.llvm.org/D80584
2020-05-31 10:46:11 -04:00
Sanjay Patel
5e9f292d99 [PhaseOrdering] add test for hoisting/CSE (PR46115); NFC 2020-05-31 10:34:18 -04:00
Simon Pilgrim
95549e7883 [X86][AVX] Add SimplifyMultipleUseDemandedBits VBROADCAST handling to SimplifyDemandedVectorElts.
As suggested on D79987.
2020-05-31 14:20:15 +01:00
Sanjay Patel
5e6d23dbb5 [VectorCombine] add tests for scalarizing binop-with-constant; NFC
Goes with proposal in D80885.

This is adapted from the InstCombine tests that were added for
D50992

But these should be adjusted further to provide more interesting
scenarios for x86-specific codegen. Eg, vector types/sizes will
have different costs depending on ISA attributes.

We also need to add tests that include a load of the scalar
variable and add tests that include extra uses of the insert
to further exercise the cost model.
2020-05-31 09:11:30 -04:00
Simon Pilgrim
ea6dbb0799 [X86] getFauxShuffleMask/getTargetShuffleInputs - make SelectionDAG const (PR45974).
Try to prevent future node creation issues (as detailed in PR45974) by making the SelectionDAG reference const, so it can still be used for analysis, but not node creation.
2020-05-31 13:51:01 +01:00
Simon Pilgrim
4f38f67fb0 [X86][AVX] Add test case described in D79987 2020-05-31 13:51:00 +01:00
Sanjay Patel
e0bbbe6290 [PhaseOrdering] add scalarization test for PR42174; NFC
Motivating test for vector-combine enhancement in D80885.
Make sure that vectorization and canonicalization are
working together as expected.
2020-05-31 08:43:34 -04:00
Simon Pilgrim
b871a92194 [X86][AVX] getFauxShuffleMask - don't widen shuffle inputs from INSERT_SUBVECTOR(X,SHUFFLE(Y,Z))
Don't create nodes on the fly when decoding INSERT_SUBVECTOR as faux shuffles.
2020-05-31 13:19:18 +01:00
Simon Pilgrim
b3bf67b5cd [X86][AVX] Pad small shuffle inputs in combineX86ShufflesRecursively
As detailed on PR45974 and D79987, getFauxShuffleMask is creating nodes on the fly to create shuffles with inputs the same size as the result, causing problems for hasOneUse() checks in later simplification stages.

Currently only combineX86ShufflesRecursively benefits from these widened inputs so I've begun moving the functionality there, and out of getFauxShuffleMask. This allows us to remove the widening from VBROADCAST and *EXTEND* faux shuffle cases.

This just leaves the INSERT_SUBVECTOR case in getFauxShuffleMask still creating nodes, which will require more extensive refactoring.
2020-05-31 11:43:47 +01:00
Florian Hahn
4c3ac27019 [ScheduleDAG] Avoid unnecessary recomputation of topological order.
In some cases ScheduleDAGRRList has to add new nodes to resolve problems
with interfering physical registers. When new nodes are added, it
completely re-computes the topological order, which can take a long
time, but is unnecessary. We only add nodes one by one, and initially
they do not have any predecessors. So we can just insert them at the end
of the vector. Later we add predecessors, but the helper function
properly updates the topological order much more efficiently. With this
change, the compile time for the program below drops from 300s to 30s on
my machine.

    define i11129 @test1() {
      %L1 = load i11129, i11129* undef
      %B30 = ashr i11129 %L1, %L1
      store i11129 %B30, i11129* undef
      ret i11129 %L1
    }

This should be generally beneficial, as we can skip a large amount of
work. Theoretically there are some scenarios where we might not safe
much, e.g. when we add a dependency between the first and last node.
Then we would have to shift all nodes. But we still do not have to spend
the time re-computing the initial order.

Reviewers: MatzeB, atrick, efriedma, niravd, paquette

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D59722
2020-05-31 11:04:35 +01:00
Kang Zhang
ad15cce54c Revert "[NFC][PowerPC] Add a new case to test phi-node-elimination pass"
This case wll be failed on some machines which enable expensive-checks.

This reverts commit af3abbf7bd2213003a133c361c212ac6efb1bd2b.
2020-05-31 09:24:21 +00:00
Kang Zhang
eb5c774879 [NFC][PowerPC] Add a new case to test phi-node-elimination pass 2020-05-31 08:05:27 +00:00
Jay Foad
8cf2c72f7d [AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS
Differential Revision: https://reviews.llvm.org/D80813
2020-05-31 05:21:55 +01:00