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Commit Graph

145 Commits

Author SHA1 Message Date
Evan Cheng
5150e3da45 MVN is addrmode1.
llvm-svn: 55530
2008-08-29 07:36:24 +00:00
Evan Cheng
c50df85672 Refactor ARM instruction format definitions into a separate file. No functionality changes.
llvm-svn: 55518
2008-08-28 23:39:26 +00:00
Dan Gohman
9742f7772d Rename SDOperand to SDValue.
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Evan Cheng
11d2c09adc Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Bill Wendling
2cae66e28b Final de-tabification.
llvm-svn: 47663
2008-02-27 06:33:05 +00:00
Chris Lattner
41717f6989 This commit changes:
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
2008-01-17 19:59:44 +00:00
Chris Lattner
6846e346a8 rename SDTRet -> SDTNone.
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
2008-01-15 22:02:54 +00:00
Chris Lattner
9b4f2b2316 get def use info more correct.
llvm-svn: 45821
2008-01-10 05:12:37 +00:00
Evan Cheng
9de4f35e9f Only mark instructions that load a single value without extension as isSimpleLoad = 1.
llvm-svn: 45727
2008-01-07 23:56:57 +00:00
Chris Lattner
14310afe42 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Chris Lattner
5489888580 rename isStore -> mayStore to more accurately reflect what it captures.
llvm-svn: 45656
2008-01-06 08:36:04 +00:00
Chris Lattner
2bb919b542 remove explicit isStore flags that are now inferrable.
llvm-svn: 45653
2008-01-06 05:55:01 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng
64a1febf9a Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
llvm-svn: 44960
2007-12-12 23:12:09 +00:00
Bill Wendling
934fcd87e7 Unifacalize the CALLSEQ{START,END} stuff.
llvm-svn: 44045
2007-11-13 09:19:02 +00:00
Bill Wendling
cc75435ebf Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
2007-11-13 00:44:25 +00:00
Owen Anderson
aba398a5ce Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
2007-11-12 07:39:39 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
Evan Cheng
24e8e4d6ef 80 col.
llvm-svn: 41812
2007-09-10 22:22:23 +00:00
Raul Herbster
49b44eae34 ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
llvm-svn: 41626
2007-08-30 23:25:47 +00:00
Evan Cheng
8c896cc115 Initial JIT support for ARM by Raul Fernandes Herbster.
llvm-svn: 40887
2007-08-07 01:37:15 +00:00
Evan Cheng
ab0a826b88 Indexed loads each has 2 outputs.
llvm-svn: 40658
2007-08-01 00:12:08 +00:00
Evan Cheng
53cb03b583 No more noResults.
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Evan Cheng
d9d3be078c No need for ccop anymore.
llvm-svn: 37965
2007-07-06 23:34:09 +00:00
Evan Cheng
3b1b3eba6a Do away with ImmutablePredicateOperand.
llvm-svn: 37961
2007-07-06 23:22:46 +00:00
Evan Cheng
c2c0b495ed PredicateDefOperand -> OptionalDefOperand.
llvm-svn: 37931
2007-07-06 01:00:49 +00:00
Evan Cheng
a59422068f Unbreak the build.
llvm-svn: 37914
2007-07-05 17:13:19 +00:00
Evan Cheng
ef8a1bcbc3 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
llvm-svn: 37895
2007-07-05 07:13:32 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Owen Anderson
89558a0db6 Fix the build.
llvm-svn: 37705
2007-06-22 16:59:54 +00:00
Evan Cheng
c49382e48f Allow predicated immediate ARM to ARM calls.
llvm-svn: 37659
2007-06-19 21:05:09 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Evan Cheng
7b433a2954 Mark these instructions clobbersPred. They modify the condition code register.
llvm-svn: 37468
2007-06-06 10:17:05 +00:00
Evan Cheng
8a52b80cdf Opcode modifier s comes after condition code. e.g. addlts, not addslt.
llvm-svn: 37388
2007-06-01 20:51:29 +00:00
Evan Cheng
c2fec89f4a Make jumptable non-predicable for now.
llvm-svn: 37381
2007-06-01 00:56:15 +00:00
Evan Cheng
5df14b3451 For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
llvm-svn: 37349
2007-05-29 23:32:06 +00:00
Dale Johannesen
f01566b705 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
llvm-svn: 37271
2007-05-21 22:42:04 +00:00
Dale Johannesen
8f484d16b0 Add some patterns for PIC PC-relative loads and stores.
llvm-svn: 37269
2007-05-21 22:14:33 +00:00
Evan Cheng
e875732104 Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
llvm-svn: 37199
2007-05-18 01:53:54 +00:00
Evan Cheng
d3f1a259db Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
llvm-svn: 37118
2007-05-16 20:50:01 +00:00
Evan Cheng
6943cefdcd Conditional branch is not a barrier.
llvm-svn: 37103
2007-05-16 07:45:54 +00:00
Evan Cheng
9f0ffdf4b3 Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Evan Cheng
73abcaa525 Switch BCC, MOVCCr, etc. to PredicateOperand.
llvm-svn: 36948
2007-05-08 21:08:43 +00:00
Dale Johannesen
0a4acbf6ac change per review
llvm-svn: 36519
2007-04-28 00:36:37 +00:00
Dale Johannesen
74feb7979a Prevent Thumb code from generating ARM instructions
llvm-svn: 36518
2007-04-27 22:17:18 +00:00
Lauro Ramos Venancio
f385b56870 ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
llvm-svn: 36506
2007-04-27 13:54:47 +00:00
Chris Lattner
87296c2580 dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll
llvm-svn: 36222
2007-04-17 22:39:58 +00:00