1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Commit Graph

45860 Commits

Author SHA1 Message Date
Che-Liang Chiou
962612fc5c ptx: add basic support of predicate execution
llvm-svn: 127569
2011-03-13 17:26:00 +00:00
Jin-Gu Kang
5000ba8961 Add comment as following:
load and store reference same memory location, the memory location
is represented by getelementptr with two uses (load and store) and
the getelementptr's base is alloca with single use. At this point,
instructions from alloca to store can be removed.
(this pattern is generated when bitfield is accessed.)
For example,
%u = alloca %struct.test, align 4               ; [#uses=1]
%0 = getelementptr inbounds %struct.test* %u, i32 0, i32 0;[#uses=2]
%1 = load i8* %0, align 4                       ; [#uses=1]
%2 = and i8 %1, -16                             ; [#uses=1]
%3 = or i8 %2, 5                                ; [#uses=1]
store i8 %3, i8* %0, align 4

llvm-svn: 127565
2011-03-13 14:05:51 +00:00
Jakob Stoklund Olesen
7d23be25ab Now that we are deleting unused live intervals during allocation, pointers may be reused.
Use the virtual register number as a cache tag instead. They are not reused.

llvm-svn: 127561
2011-03-13 01:29:32 +00:00
Jakob Stoklund Olesen
2d87d5139b Tell the register allocator about new unused virtual registers.
This allows the allocator to free any resources used by the virtual register,
including physical register assignments.

llvm-svn: 127560
2011-03-13 01:23:11 +00:00
Oscar Fuentes
208de1fcc4 Build CompilerDriver library.
llvm-svn: 127554
2011-03-12 22:01:42 +00:00
Benjamin Kramer
5986a24bae Teach ComputeMaskedBits about sub nsw.
llvm-svn: 127548
2011-03-12 17:18:11 +00:00
Duncan Sands
0514e10276 Speculatively revert commit 127478 (jsjodin) in an attempt to fix the
llvm-gcc-i386-linux-selfhost and llvm-x86_64-linux-checks buildbots.
The original log entry:
Remove optimization emitting a reference insted of label difference, since
it can create more relocations. Removed isBaseAddressKnownZero method,
because it is no longer used.

llvm-svn: 127540
2011-03-12 13:07:37 +00:00
Jin-Gu Kang
5e537a9449 This patch removes some of useless instructions generated by bitfield access.
llvm-svn: 127539
2011-03-12 12:18:44 +00:00
Jakob Stoklund Olesen
6d02ddbbc3 Include snippets in the live stack interval.
llvm-svn: 127530
2011-03-12 04:25:36 +00:00
Jakob Stoklund Olesen
1f9f236b8a Spill multiple registers at once.
Live range splitting can create a number of small live ranges containing only a
single real use. Spill these small live ranges along with the large range they
are connected to with copies. This enables memory operand folding and maximizes
the spill to fill distance.

Work in progress with known bugs.

llvm-svn: 127529
2011-03-12 04:17:20 +00:00
Sean Callanan
4f6e58ff09 Fixed the comparison operator for the enhanced
disassembler's disassembler map.

llvm-svn: 127527
2011-03-12 03:27:54 +00:00
Jakob Stoklund Olesen
925b25d53d That's it, I am declaring this a failure of the C++03 STL.
There are too many compatibility problems with using mixed types in
std::upper_bound, and I don't want to spend 110 lines of boilerplate setting up
a call to a 10-line function. Binary search is not /that/ hard to implement
correctly.

I tried terminating the binary search with a linear search, but that actually
made the algorithm slower against my expectation. Most live intervals have less
than 4 segments. The early test against endIndex() does pay, and this version is
25% faster than plain std::upper_bound().

llvm-svn: 127522
2011-03-12 01:50:35 +00:00
Eric Christopher
80a45901e0 Sometimes isPredicable lies to us and tells us we don't need the operands.
Go ahead and add them on when we might want to use them and let
later passes remove them.

Fixes rdar://9118569

llvm-svn: 127518
2011-03-12 01:09:29 +00:00
Jim Grosbach
f7531e7697 Add FIXME.
llvm-svn: 127516
2011-03-12 00:51:00 +00:00
Jim Grosbach
555d910477 Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.

llvm-svn: 127515
2011-03-12 00:45:26 +00:00
Jim Grosbach
923c731f15 Add a FIXME.
llvm-svn: 127511
2011-03-11 23:25:21 +00:00
Jim Grosbach
daffeb06fb Pseudo-ize the ARM 'B' instruction.
llvm-svn: 127510
2011-03-11 23:24:15 +00:00
Jim Grosbach
2226dfbea2 Remove dead code. These ARM instruction definitions no longer exist.
llvm-svn: 127509
2011-03-11 23:15:02 +00:00
Jim Grosbach
009af69d6d Pseudo-ize VMOVDcc and VMOVScc.
llvm-svn: 127506
2011-03-11 23:09:50 +00:00
Jim Grosbach
61ff87cd2d 80 columns
llvm-svn: 127505
2011-03-11 23:00:16 +00:00
Jim Grosbach
27eaca3e0d Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
effect that we get proper instruction printing using the "pop" mnemonic for it.

llvm-svn: 127502
2011-03-11 22:51:41 +00:00
Cameron Zwarich
bf5c9cd119 Roll r127459 back in:
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127498
2011-03-11 21:52:04 +00:00
Cameron Zwarich
39a49276db Fix the GCC test suite issue exposed by r127477, which was caused by stack
protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.

llvm-svn: 127497
2011-03-11 21:51:56 +00:00
Owen Anderson
78afadfa5d Teach FastISel to support register-immediate-immediate instructions.
llvm-svn: 127496
2011-03-11 21:33:55 +00:00
Jim Grosbach
ee6075cda5 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489
2011-03-11 20:44:08 +00:00
Jim Grosbach
3329263352 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
and VDUPLN32d, respectively.

llvm-svn: 127486
2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485
2011-03-11 20:18:05 +00:00
Jim Grosbach
fff6ff502b This FIXME has been fixed.
llvm-svn: 127483
2011-03-11 20:07:37 +00:00
Jim Grosbach
2ecded3a94 Properly pseudo-ize ARM MVNCCi.
llvm-svn: 127482
2011-03-11 19:55:55 +00:00
Jan Sjödin
b58b9618ce Remove optimization emitting a reference insted of label difference, since it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used.
llvm-svn: 127478
2011-03-11 19:37:02 +00:00
Daniel Dunbar
a02706c889 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
created from the", it broke some GCC test suite tests.

llvm-svn: 127477
2011-03-11 19:30:30 +00:00
Jim Grosbach
39804c0b44 Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).
llvm-svn: 127469
2011-03-11 18:00:42 +00:00
Andrew Trick
6aa37a4a2b Replace -dag-chain-limit flag with constant. It has survived a release cycle without being touched, so no longer needs to pollute the hidden-help text.
llvm-svn: 127468
2011-03-11 17:46:59 +00:00
Benjamin Kramer
d4ea449e7e ComputeMaskedBits: sub falls through to add, and sub doesn't have the same overflow semantics as add.
Should fix the selfhost failures that started with r127463.

llvm-svn: 127465
2011-03-11 14:46:49 +00:00
Benjamin Kramer
666407939f InstCombine: Fix a thinko where transform an icmp under the assumption that it's a zero comparison when it's not.
Fixes PR9454.

llvm-svn: 127464
2011-03-11 11:37:40 +00:00
Nick Lewycky
cf0e3e88df Teach ComputeMaskedBits about nsw on add. I don't think there's anything we can
do with nuw here, but sub and mul should be given similar treatment.
Fixes PR9343 #15!

llvm-svn: 127463
2011-03-11 09:00:19 +00:00
John Wiegley
e1168a569b Fix use of CompEnd predicate to be standards conforming
The existing CompEnd predicate does not define a strict weak order as required
by the C++03 standard; therefore, its use as a predicate to std::upper_bound
is invalid. For a discussion of this issue, see
http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#270

This patch replaces the asymmetrical comparison with an iterator adaptor that
achieves the same effect while being strictly standard-conforming by ensuring
an apples-to-apples comparison.

llvm-svn: 127462
2011-03-11 08:54:34 +00:00
Cameron Zwarich
9ed726c151 Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127459
2011-03-11 04:54:27 +00:00
Chris Lattner
2cd24b852f silence a conditional assignment -Wuninitialized warning.
llvm-svn: 127453
2011-03-11 02:12:51 +00:00
Jim Grosbach
ed45ac390c Properly pseudo-ize ARM MOVCCi and MOVCCi16.
llvm-svn: 127442
2011-03-11 01:09:28 +00:00
Eric Christopher
46f43c9cce Change the x86 32-bit scheduler to register pressure and fix up the
corresponding testcases back to the previous versions.

Fixes some performance regressions only seen on 32-bit.

llvm-svn: 127441
2011-03-11 01:05:58 +00:00
Evan Cheng
d5d2d4a158 Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613.
llvm-svn: 127440
2011-03-11 00:48:56 +00:00
Jim Grosbach
1986d9ac8f Properly pseudo-ize MOVCCr and MOVCCs.
llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Dan Gohman
051cc738c3 RecursivelyDeleteTriviallyDeadInstructions only needs a
Value, not an Instruction, so casting is not necessary. Also,
it's theoretically possible that the Value is not an
Instruction, since WeakVH follows RAUWs.

llvm-svn: 127427
2011-03-10 20:57:44 +00:00
Rafael Espindola
222ccb2bdd Don't compute the file size if we don't need to.
llvm-svn: 127426
2011-03-10 20:54:07 +00:00
Dan Gohman
bb9c77f5bd Fix reassociate to postpone certain instruction deletions until
after it has finished all of its reassociations, because its
habit of unlinking operands and holding them in a datastructure
while working means that it's not easy to determine when an
instruction is really dead until after all its regular work is
done. rdar://9096268.

llvm-svn: 127424
2011-03-10 19:51:54 +00:00
Jim Grosbach
5891b1323a DMB can just be a pat referencing MCR.
llvm-svn: 127423
2011-03-10 19:27:17 +00:00
Jim Grosbach
4b74ef6ca9 Reorganize a bit. No functional change, just moving patterns up.
llvm-svn: 127422
2011-03-10 19:21:08 +00:00
Jim Grosbach
db549a7f6c Pseudo-instructions are codegenonly by definition.
llvm-svn: 127420
2011-03-10 19:06:39 +00:00
Benjamin Kramer
52a44b9c80 InstCombine: Turn umul_with_overflow into mul nuw if we can prove that it cannot overflow.
This happens a lot in clang-compiled C++ code because it adds overflow checks to operator new[]:
  unsigned *foo(unsigned n) { return new unsigned[n]; }
We can optimize away the overflow check on 64 bit targets because (uint64_t)n*4 cannot overflow.

llvm-svn: 127418
2011-03-10 18:40:14 +00:00