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17 Commits

Author SHA1 Message Date
Elena Demikhovsky
d8fd06be73 AVX-512: Fixed the "test" operation for i1 type 
Using KORTESTW for comparison i1 value with zero was wrong since the instruction tests 16 bits.
KORTESTW may be used with KSHIFTL+KSHIFTR that clean the 15 upper bits.
I removed (X86cmp i1, 0) pattern and zero-extend i1 to i8 and then use TESTB.

There are some cases where i1 is in the mask register and the upper bits are already zeroed.
Then KORTESTW is the better solution, but it is subject for optimization.
Meanwhile, I'm fixing the correctness issue.

llvm-svn: 228916
 2015-02-12 08:40:34 +00:00
Elena Demikhovsky
6889f421a2 AVX-512: Changes in operations on masks registers for KNL and SKX 
- Added KSHIFTB/D/Q for skx
- Added KORTESTB/D/Q for skx
- Fixed store operation for v8i1 type for KNL
- Store size of v8i1, v4i1 and v2i1 are changed to 8 bits

llvm-svn: 227043
 2015-01-25 12:47:15 +00:00
Adam Nemet
e7c4f25494 [AVX512] Add DQ subvector inserts 
In AVX512f we support 64x2 and 32x8 inserts via matching them to 32x4 and 64x4
respectively.  These are matched by "Alt" Pat<>'s (Alt stands for alternative
VTs).

Since DQ has native support for these intructions, I peeled off the non-"Alt"
part of the baseclass into vinsert_for_size_no_alt. The DQ instructions are
derived from this multiclass.  The "Alt" Pat<>'s are disabled with DQ.

Fixes <rdar://problem/18426089>

llvm-svn: 219874
 2014-10-15 23:42:17 +00:00
Adam Nemet
295cdb726c [AVX512] Add SKX testing to avx512-insert-extract.ll 
This is in preparation to adding DQ subvector inserts to this testcase.

llvm-svn: 219873
 2014-10-15 23:42:14 +00:00
Adam Nemet
517a59b132 [AVX512] Fix test to produce a defined value 
We're inserting into a 8 wide vector, so the index should be < 8.

llvm-svn: 219872
 2014-10-15 23:42:11 +00:00
Adam Nemet
ffc86b5e73 [AVX512] Make vextract*x4/vinsert*x4 tests check for the index as well 
Extend test so that it provides coverage for the next commit.

llvm-svn: 218479
 2014-09-25 23:48:47 +00:00
Elena Demikhovsky
56ab81fd87 AVX-512: insert element to mask vector; store i1 data 
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type

llvm-svn: 205850
 2014-04-09 12:37:50 +00:00
Elena Demikhovsky
838b163a58 AVX-512: Fixed extract_vector_elt for v8i1 vector 
llvm-svn: 202624
 2014-03-02 09:19:44 +00:00
Elena Demikhovsky
2cdad2b3d4 AVX-512: simpyfied BUILD_VECTOR for masks; fixed cmp/test sequence 
llvm-svn: 201487
 2014-02-16 11:34:23 +00:00
Elena Demikhovsky
110d93ce93 AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors. 
llvm-svn: 201066
 2014-02-10 07:02:39 +00:00
Elena Demikhovsky
b43ccbc3f7 AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384
 2013-12-16 13:52:35 +00:00
Elena Demikhovsky
154413adc2 AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC. 
I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll
I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions).

llvm-svn: 197041
 2013-12-11 14:31:04 +00:00
Elena Demikhovsky
bac904c06d AVX-512: Handled extractelement from mask vector; 
Added VMOSHDUP/VMOVSLDUP shuffle instructions.

llvm-svn: 194691
 2013-11-14 11:29:27 +00:00
Elena Demikhovsky
139f25ed2c AVX-512: implemented extractelement with variable index. 
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.

llvm-svn: 190595
 2013-09-12 08:55:00 +00:00
Stephen Lin
ec70f360f9 CHECK-LABEL-ify tests 
llvm-svn: 188087
 2013-08-09 17:50:15 +00:00
Elena Demikhovsky
2f33e9fa89 AVX-512 set: added VEXTRACTPS instruction 
llvm-svn: 187705
 2013-08-04 10:46:07 +00:00
Elena Demikhovsky
175a2e60dd Added INSERT and EXTRACT intructions from AVX-512 ISA. 
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.

llvm-svn: 187491
 2013-07-31 11:35:14 +00:00