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3031 Commits

Author SHA1 Message Date
Michael J. Spencer
98ad3f2ea7 CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally. 
llvm-svn: 113632
 2010-09-10 21:14:25 +00:00
Bob Wilson
027c57accb Calculate the number of VLDM/VSTM registers by subtracting the number of 
fixed operands from the total number of operands (including the variadic ones).

llvm-svn: 113597
 2010-09-10 18:25:35 +00:00
Bill Wendling
6cc7baa725 Reword since this may not be a bug but intended behavior. 
llvm-svn: 113584
 2010-09-10 10:31:11 +00:00
Bob Wilson
01b7bf3510 Fix merging base-updates for VLDM/VSTM: Before I switched these instructions 
to use AddrMode4, there was a count of the registers stored in one of the
operands.  I changed that to just count the operands but forgot to adjust for
the size of D registers.  This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.

llvm-svn: 113576
 2010-09-10 05:15:04 +00:00
Evan Cheng
c9cb37516d Teach if-converter to be more careful with predicating instructions that would 
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.

llvm-svn: 113570
 2010-09-10 01:29:16 +00:00
Eric Christopher
54e138031e Fix build error. 
llvm-svn: 113566
 2010-09-10 00:35:09 +00:00
Eric Christopher
92506682eb Update comments, reorganize some code, rename variables to be 
more clear.  No functional change.

llvm-svn: 113565
 2010-09-10 00:34:35 +00:00
Eric Christopher
06f4af2ef4 64-bit fp loads can come straight out of the constant pool, not as 
bad as I'd thought.

llvm-svn: 113561
 2010-09-09 23:50:00 +00:00
Eric Christopher
3c86728bd6 SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move 
some data around and implement a couple of move routines to do this.

llvm-svn: 113546
 2010-09-09 21:44:45 +00:00
Eric Christopher
d5f271d31e New "move to fp reg" routine. Use it. 
llvm-svn: 113537
 2010-09-09 20:49:25 +00:00
Eric Christopher
7208671884 "Strike that, reverse it." -- Mr. Wonka. 
Truncate when truncating, extend when extending.

llvm-svn: 113536
 2010-09-09 20:36:19 +00:00
Eric Christopher
38194e51cc Add FPTrunc, fix some bugs where I forgot to update the value map. 
llvm-svn: 113533
 2010-09-09 20:26:31 +00:00
Eric Christopher
2ba28d3889 Basic FP->Int, Int->FP conversions. 
llvm-svn: 113523
 2010-09-09 18:54:59 +00:00
Evan Cheng
b79a03a3ca For each instruction itinerary class, specify the number of micro-ops each 
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513
 2010-09-09 18:18:55 +00:00
Bob Wilson
524123343c Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from 
the VST pseudos.  The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.

llvm-svn: 113473
 2010-09-09 05:40:26 +00:00
Eric Christopher
e5bf22fd67 Nuke whitespace and fix some indenting. 
llvm-svn: 113463
 2010-09-09 01:06:51 +00:00
Eric Christopher
8c3a582b5f Handle 64-bit floating point binops as well. 
llvm-svn: 113461
 2010-09-09 01:02:03 +00:00
Eric Christopher
f2f2b06719 Basic 32-bit FP operations. 
llvm-svn: 113459
 2010-09-09 00:53:57 +00:00
Bob Wilson
2b284b178f For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use 
operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.

llvm-svn: 113456
 2010-09-09 00:38:32 +00:00
Eric Christopher
88c13fcb96 Handle float->double extension. 
llvm-svn: 113455
 2010-09-09 00:26:48 +00:00
Eric Christopher
ebfbac39cf Rewrite TargetMaterializeConstant splitting it out into two functions 
for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.

llvm-svn: 113453
 2010-09-09 00:19:41 +00:00
Bob Wilson
92b5646145 Simplify copying over operands from pseudo NEON load/store instructions. 
For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.

llvm-svn: 113452
 2010-09-09 00:15:32 +00:00
Bob Wilson
97c066dfac Clean up a comment. 
llvm-svn: 113442
 2010-09-08 23:39:54 +00:00
Eric Christopher
66c62991e0 Very basic compare support. 
llvm-svn: 113440
 2010-09-08 23:13:45 +00:00
Eric Christopher
2a86c17b8d Delete dead code. 
llvm-svn: 113436
 2010-09-08 22:58:35 +00:00
Evan Cheng
b87520ca74 Fix LDM_RET schedule itinery. 
llvm-svn: 113435
 2010-09-08 22:57:08 +00:00
Eric Christopher
bc029c3eb0 Make the loads/stores match the type we really want to store. 
llvm-svn: 113417
 2010-09-08 21:49:50 +00:00
Jim Grosbach
0f01a7319e Re-enable usage of the ARM base pointer. r113394 fixed the known failures. 
Re-running some nightly testers w/ it enabled to verify.

llvm-svn: 113399
 2010-09-08 20:12:02 +00:00
Jim Grosbach
e709eae92e Fix errant fall-throughs causing the base pointer to be used when the frame 
pointer was intended. rdar://8401980

llvm-svn: 113394
 2010-09-08 19:55:28 +00:00
Eric Christopher
4108aae8d3 Rewrite TargetMaterializeConstant. 
llvm-svn: 113387
 2010-09-08 18:56:34 +00:00
Jim Grosbach
273fed4827 Be more careful about when to do dynamic stack realignment. Since we have an 
option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).

llvm-svn: 113366
 2010-09-08 17:22:12 +00:00
Jim Grosbach
5411e69cbd Add missing assert 
llvm-svn: 113365
 2010-09-08 17:05:45 +00:00
Chris Lattner
0e0f9094e9 change the MC "ParseInstruction" interface to make it the 
implementation's job to check for and lex the EndOfStatement
marker.

llvm-svn: 113347
 2010-09-08 05:10:46 +00:00
NAKAMURA Takumi
e223d51276 ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255. 
llvm-svn: 113345
 2010-09-08 04:48:17 +00:00
Jim Grosbach
6aba2dc40a remove trailing whitespace 
llvm-svn: 113338
 2010-09-08 03:54:02 +00:00
Jim Grosbach
9e69f92835 remove obsolete comment 
llvm-svn: 113337
 2010-09-08 03:51:44 +00:00
Jim Grosbach
7a957dc761 disable for the moment while tracking down a few Thumb2-O0 failure that look 
related. (attempt deux, complete w/ test update this time)

llvm-svn: 113333
 2010-09-08 02:00:34 +00:00
Jim Grosbach
31f79e5d47 woops. need to update a test along with this. 
llvm-svn: 113332
 2010-09-08 01:49:09 +00:00
Jim Grosbach
89098087dd disable temporarily while sorting out a few test failures in Thumb2-O0 tests. 
llvm-svn: 113331
 2010-09-08 01:47:49 +00:00
Jim Grosbach
e1ea3730f4 correct spill code to properly determine if dynamic stack realignment is 
present in the function and thus whether aligned load/store instructions can
be used.

llvm-svn: 113323
 2010-09-08 00:26:59 +00:00
Jim Grosbach
27a5b1fd3b VFP/NEON load/store multiple instructions are addrmode4, not 5. 
llvm-svn: 113322
 2010-09-08 00:25:50 +00:00
Jim Grosbach
5d310ec4a5 To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the base 
register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).

rdar://8394087

llvm-svn: 113297
 2010-09-07 22:30:53 +00:00
Jim Grosbach
b40371d3bf grammar tweak 
llvm-svn: 113289
 2010-09-07 21:30:25 +00:00
Chris Lattner
7b50cefea8 hopefully fix a problem building on cygwin-1.5 
llvm-svn: 113255
 2010-09-07 19:50:53 +00:00
Chris Lattner
6bfa0d9988 in the case where an instruction only has one implementation 
of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178
 2010-09-06 22:11:18 +00:00
Chris Lattner
22bb9cb511 change MatchInstructionImpl to return an enum instead of bool. 
llvm-svn: 113165
 2010-09-06 19:22:17 +00:00
Chris Lattner
45a204be76 have AsmMatcherEmitter.cpp produce the hunk of code that gets included 
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.

llvm-svn: 113163
 2010-09-06 19:11:01 +00:00
Chris Lattner
c0e5368884 remove some dead code. t2addrmode_imm8s4 is never used in a 
pattern, so there is no need to define a matching function.

llvm-svn: 113122
 2010-09-05 22:51:11 +00:00
Chris Lattner
bd47c48735 cleanups. 
llvm-svn: 113119
 2010-09-05 21:18:45 +00:00
Chris Lattner
8df3ffd7ac zap dead code. 
llvm-svn: 113073
 2010-09-04 18:12:00 +00:00