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Commit Graph

90811 Commits

Author SHA1 Message Date
Sean Silva
61ad8bcdeb [docs] Reorganize mailing lists.
Order them roughly by "which one should a newbie join first".

llvm-svn: 178424
2013-03-30 15:32:54 +00:00
Sean Silva
7a23f14fdb [docs] Pull IRC and Mailing Lists under a new "Community" heading.
llvm-svn: 178423
2013-03-30 15:32:51 +00:00
Sean Silva
dd29200a97 [docs] The GEP FAQ is not "design and overview"
llvm-svn: 178422
2013-03-30 15:32:50 +00:00
Sean Silva
b35b1c47e9 [docs] Put DeveloperPolicy under "Development Process Documentation"
llvm-svn: 178421
2013-03-30 15:32:47 +00:00
Benjamin Kramer
19e3b89136 Put private class into an anonmyous namespace.
llvm-svn: 178420
2013-03-30 15:23:08 +00:00
Justin Holewinski
21480942b2 [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.
llvm-svn: 178417
2013-03-30 14:29:30 +00:00
Justin Holewinski
23056edada [NVPTX] Add NVVMReflect pass to allow compile-time selection of
specific code paths.

This allows us to write code like:

  if (__nvvm_reflect("FOO"))
    // Do something
  else
    // Do something else

and compile into a library, then give "FOO" a value at kernel
compile-time so the check becomes a no-op.

llvm-svn: 178416
2013-03-30 14:29:25 +00:00
Justin Holewinski
707786b174 [NVPTX] Run clang-format on all NVPTX sources.
Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.

llvm-svn: 178415
2013-03-30 14:29:21 +00:00
Benjamin Kramer
1b48942ea8 Object: Turn a couple of degenerate for loops into while loops.
No functionality change.

llvm-svn: 178413
2013-03-30 13:07:51 +00:00
Shuxin Yang
c53fc5dc4c Implement XOR reassociation. It is based on following rules:
rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2),
     only useful when c1=c2
  rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2))
  rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2
  rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2

 It reduces an application's size (in terms of # of instructions) by 8.9%.
 Reviwed by Pete Cooper. Thanks a lot!

 rdar://13212115  

llvm-svn: 178409
2013-03-30 02:15:01 +00:00
Akira Hatanaka
bc81d23802 [mips] Add patterns for DSP indexed load instructions.
llvm-svn: 178408
2013-03-30 02:14:45 +00:00
Akira Hatanaka
fd5850047c [mips] Define reg+imm load/store pattern templates.
llvm-svn: 178407
2013-03-30 02:01:48 +00:00
Akira Hatanaka
5ff9493456 [mips] Fix DSP instructions to have explicit accumulator register operands.
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.

llvm-svn: 178406
2013-03-30 01:58:00 +00:00
Akira Hatanaka
7573219c13 Remove unused variables.
llvm-svn: 178405
2013-03-30 01:46:28 +00:00
Akira Hatanaka
6c9ddf6943 [mips] Move the code which does dag-combine for multiply-add/sub nodes to
derived class MipsSETargetLowering.

We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.

llvm-svn: 178404
2013-03-30 01:42:24 +00:00
Akira Hatanaka
b8c6fcef56 [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.

llvm-svn: 178403
2013-03-30 01:36:35 +00:00
Akira Hatanaka
01ec458f56 [mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.
llvm-svn: 178396
2013-03-30 01:16:38 +00:00
Akira Hatanaka
106cf732df Fix indentation.
llvm-svn: 178395
2013-03-30 01:15:17 +00:00
Akira Hatanaka
33684b1e2e [mips] Add mips-specific nodes which will be used to select multiply and divide
instructions.

llvm-svn: 178394
2013-03-30 01:14:04 +00:00
Akira Hatanaka
aa7cae6b45 [mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is
called in several places in ScheduleDAGRRList.cpp.

llvm-svn: 178393
2013-03-30 01:12:05 +00:00
Akira Hatanaka
438e940329 [mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStack
to handle accumulator registers.

llvm-svn: 178392
2013-03-30 01:08:05 +00:00
Akira Hatanaka
51b8645403 [mips] Expand pseudo load, store and copy instructions right before
callee-saved scan.

The code makes use of register's scavenger's capability to spill multiple
registers.

llvm-svn: 178391
2013-03-30 01:04:11 +00:00
Akira Hatanaka
86302e607d [mips] Define pseudo instructions for spilling and copying accumulator
registers.

llvm-svn: 178390
2013-03-30 00:54:52 +00:00
Eric Christopher
05df599ea8 Use SmallVectorImpl instead of SmallVector at the uses.
llvm-svn: 178386
2013-03-29 23:34:06 +00:00
Bob Wilson
7e366d2845 Run the ObjCARCContract pass for LTO. <rdar://problem/13538084>
llvm-svn: 178385
2013-03-29 23:28:55 +00:00
Michael Gottesman
1bc2d353ed Updated test0 of retain-not-declared.ll to reflect the fact that objc-arc-expand runs before objc-arc/objc-arc-contract.
Specifically, objc-arc-expand will make sure that the
objc_retainAutoreleasedReturnValue, objc_autoreleaseReturnValue, and ret
will all have %call as an argument.

llvm-svn: 178382
2013-03-29 22:44:59 +00:00
Jean-Luc Duprat
7776961622 SmallVector and SmallPtrSet allocations now power-of-two aligned.
This time tested on both OSX and Linux.

llvm-svn: 178377
2013-03-29 22:07:12 +00:00
Sean Silva
04c7342f29 [docs] The STL "binary search" has a non-obvious name.
std::lower_bound is the canonical "binary search" in the STL
(std::binary_search generally is not what you want). The name actually
makes a lot of sense (and also has a beautiful symmetry with the
std::upper_bound algorithm). The name is nonetheless non-obvious.

Also, remove mention of "radix search". It's not even clear how that
would work in the context of a sorted vector. AFAIK "radix search" only
makes sense when you have a trie-like data structure.

llvm-svn: 178376
2013-03-29 21:57:47 +00:00
Timur Iskhodzhanov
d7d35221f7 Exclude the X86/complex-fca.ll test at it probably wasn't supposed to work on Windows
llvm-svn: 178375
2013-03-29 21:54:00 +00:00
Michael Gottesman
c7ef28e19f Add clang.arc.used to ModuleHasARC so ARC always runs if said call is present in a module.
clang.arc.used is an interesting call for ARC since ObjCARCContract
needs to run to remove said intrinsic to avoid a linker error (since the
call does not exist).

llvm-svn: 178369
2013-03-29 21:15:23 +00:00
Jyotsna Verma
91f1858936 Hexagon: Add emitFrameIndexDebugValue function to emit debug information.
llvm-svn: 178368
2013-03-29 21:09:53 +00:00
Eric Christopher
cd1e668cce Use 12 as the magic number for our abbreviation data and our
die values. A lot of DIEs have 10 attributes in C++ code (example
clang), none had more than 12. Seems like a good default.

llvm-svn: 178366
2013-03-29 20:23:06 +00:00
Eric Christopher
4658dc0478 Move the construction of the skeleton compile unit after the
entire original compile unit has been constructed.

llvm-svn: 178365
2013-03-29 20:23:02 +00:00
Adrian Prantl
dd8a6dc41a move testcase into appropriate X86 subdirectory.
llvm-svn: 178364
2013-03-29 20:14:08 +00:00
Hal Finkel
c14a74d243 Implement FRINT lowering on PPC using frin
Like nearbyint, rint can be implemented on PPC using the frin instruction. The
complication comes from the fact that rint needs to set the FE_INEXACT flag
when the result does not equal the input value (and frin does not do that). As
a result, we use a custom inserter which, after the rounding, compares the
rounded value with the original, and if they differ, explicitly sets the XX bit
in the FPSCR register (which corresponds to FE_INEXACT).

Once LLVM has better modeling of the floating-point environment we should be
able to (often) eliminate this extra complexity.

llvm-svn: 178362
2013-03-29 19:41:55 +00:00
Akira Hatanaka
251bd9f852 [mips] Define a function which returns the GPR register class.
llvm-svn: 178359
2013-03-29 19:17:42 +00:00
Andrew Trick
4e1ed3a6dc Fix TableGen subtarget-emitter to handle A9/Swift.
A9 uses itinerary classes, Swift uses RW lists. This tripped some
verification when we're expanding variants. I had to refine the
verification a bit.

llvm-svn: 178357
2013-03-29 19:08:31 +00:00
Matt Arsenault
fe0553b737 Build fixes for STLPort + GCC
llvm-svn: 178356
2013-03-29 18:48:45 +00:00
Matt Arsenault
ec92115e0d Fix loop style
llvm-svn: 178355
2013-03-29 18:48:42 +00:00
Adrian Prantl
324e4868cb Split the llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m testcase into a CFE and LLVM part.
rdar://problem/12767564

llvm-svn: 178353
2013-03-29 18:08:14 +00:00
Benjamin Kramer
279e5cfa9a Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.

llvm-svn: 178349
2013-03-29 17:14:24 +00:00
Nadav Rotem
6d5518d53d Fix a typo
llvm-svn: 178346
2013-03-29 16:34:23 +00:00
Jyotsna Verma
c91629764d Hexagon: Disable DwarfUsesInlineInfoSection flag.
llvm-svn: 178345
2013-03-29 15:46:12 +00:00
Hal Finkel
3493fd8e51 Add PPC FP rounding instructions fri[mnpz]
These instructions are available on the P5x (and later) and on the A2. They
implement the standard floating-point rounding operations (floor, trunc, etc.).
One caveat: frin (round to nearest) does not implement "ties to even", and so
is only enabled in fast-math mode.

llvm-svn: 178337
2013-03-29 08:57:48 +00:00
Rafael Espindola
e78555387c Revert "Fix allocations of SmallVector and SmallPtrSet so they are more prone to"
This reverts commit 617330909f0c26a3f2ab8601a029b9bdca48aa61.

It broke the bots:

/home/clangbuild2/clang-ppc64-2/llvm.src/unittests/ADT/SmallVectorTest.cpp:150: PushPopTest
/home/clangbuild2/clang-ppc64-2/llvm.src/unittests/ADT/SmallVectorTest.cpp:118: Failure
Value of: v[i].getValue()
  Actual: 0
Expected: value
Which is: 2

llvm-svn: 178334
2013-03-29 07:11:21 +00:00
Jean-Luc Duprat
0ba254f23f Fix allocations of SmallVector and SmallPtrSet so they are more prone to
being power-of-two sized.

llvm-svn: 178332
2013-03-29 05:45:22 +00:00
Michael Gottesman
6eceba6dde Removed trailing whitespace.
llvm-svn: 178329
2013-03-29 05:13:07 +00:00
Akira Hatanaka
b8d0cfec7c [mips] Change type of accumulator registers to Untyped. Add two more accumulator
register classes for Mips64 and DSP-ASE.

No functionality changes.

llvm-svn: 178328
2013-03-29 03:27:21 +00:00
Akira Hatanaka
fe61de70c1 [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.
No functionality changes.

llvm-svn: 178327
2013-03-29 02:14:12 +00:00
Akira Hatanaka
c27c81aa86 [mips] Add parameter Alignment to MipsFrameLowering's constructor.
No functionality changes.

llvm-svn: 178326
2013-03-29 01:51:04 +00:00