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1033 Commits

Author SHA1 Message Date
Zoran Jovanovic
618c7b08b2 Test case micromips-load-effective-address.s renamed to micromips-load-effective-address.ll and moved to test/CodeGen/Mips. 
llvm-svn: 199221
 2014-01-14 16:26:47 +00:00
Rafael Espindola
8113c62abe Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips". 
This matches what gnu as does and implementing this is easier than arguing
about it.

llvm-svn: 199181
 2014-01-14 04:25:13 +00:00
Jack Carter
4a5987eef3 [Mips] TargetStreamer Support for .abicalls and .set pic0. 
This patch adds .abicalls and .set pic0 support which
affects the ELF ABI and its flags. In addition the patch uses
a common interface for both the MipsTargetSteamer and
MipsObjectStreamer that both the integrated and standalone
assemblers will use for the output for these directives.

llvm-svn: 198646
 2014-01-06 23:27:31 +00:00
Zoran Jovanovic
f9d8ca7036 Support for microMIPS load effective address. 
llvm-svn: 198010
 2013-12-25 10:14:07 +00:00
Zoran Jovanovic
427d20b793 Support for microMIPS FPU instructions 2. 
llvm-svn: 198009
 2013-12-25 10:09:27 +00:00
Zoran Jovanovic
b55909330e Support for microMIPS FPU instructions 1. 
llvm-svn: 197815
 2013-12-20 15:44:08 +00:00
Zoran Jovanovic
e6baed485f Support for microMIPS control instructions. 
llvm-svn: 197696
 2013-12-19 16:25:00 +00:00
Zoran Jovanovic
a4d6da998d Support for microMIPS LL and SC instructions. 
llvm-svn: 197692
 2013-12-19 16:12:56 +00:00
Zoran Jovanovic
6b16ca6dfa Support for microMIPS TLS relocations. 
llvm-svn: 197685
 2013-12-19 16:02:32 +00:00
Matheus Almeida
351a06901f [mips][msa] Update format of RUN lines for every MSA MC test. 
1. The arch directive now appears before the cpu directive
2. Long run lines were split across multiple lines
    
No functional changes.

llvm-svn: 197588
 2013-12-18 17:31:21 +00:00
Matheus Almeida
25c76494df [mips][msa] Remove unneeded triple directive in MSA MC tests. 
No functional changes.

llvm-svn: 197559
 2013-12-18 11:06:13 +00:00
Matheus Almeida
b7efcc666c [mips] Fix off by one issue when applying a fixup. 
The branch offset for a R_MIPS_PC16 relocation is indeed a 16-bit signed
immediate.

llvm-svn: 197506
 2013-12-17 17:10:00 +00:00
Matheus Almeida
b273b4d798 [mips] Add checks for alignment and maximum displacements for most of the 
branch instructions for mips and micromips instruction sets thus avoiding
the situation of generating branches to undesired locations if offsets
cannot be encoded.

This patch also checks if a fixup cannot be applied and returns a fatal error
if that's the case.

llvm-svn: 197223
 2013-12-13 11:11:02 +00:00
Vladimir Medic
4d40c9969e Method parseSetAssignment treats every operand with '$' sign as register and the parsing is directed to set alias for register. This will result in errors reported when expressions containing label references are parsed(for example long jumps) 
As we can't make a complete solution now it has been decided to enable .set directive to handle long jump expressions. This will cause parser to report errors when parsing integer based register assignments, for example:
   .set r3, will be reported as error. Still, the need for expressions is higher priority as the integer based register assignments are Mips specific and can be avoided using register names.

llvm-svn: 196773
 2013-12-09 11:03:25 +00:00
Matheus Almeida
f0fc3cf095 [mips][msa] Fix issue with immediate fields of LD/ST instructions 
not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.

llvm-svn: 196494
 2013-12-05 11:06:22 +00:00
Zoran Jovanovic
335dc8689e Test case for issue with microMIPS long branch. 
llvm-svn: 195976
 2013-11-30 19:13:15 +00:00
Zoran Jovanovic
b8cffe14c6 Revert revision 195965. 
llvm-svn: 195967
 2013-11-29 22:10:02 +00:00
Zoran Jovanovic
797919cb22 Fixed issue with microMIPS long branch. 
llvm-svn: 195965
 2013-11-29 21:41:24 +00:00
Jack Carter
6943b6e5c6 reverts 195057 per request 
llvm-svn: 195152
 2013-11-19 20:53:28 +00:00
Jack Carter
8bb31d387d [Mips] Support for MicroMips STO refactoring. 
No true functional changes.

Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.

Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.

XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.

llvm-svn: 195067
 2013-11-19 01:25:18 +00:00
Matheus Almeida
a941fd6ccd [mips][msa] Update encoding of bnz.v (typo). 
Note that there's no hardware yet that relies on that encoding.

llvm-svn: 195006
 2013-11-18 13:09:54 +00:00
Matheus Almeida
f3405464c6 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded. 
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.

llvm-svn: 195004
 2013-11-18 12:32:49 +00:00
Zoran Jovanovic
e87258135d Use instr mapping for microMIPS in llvm-mc. 
llvm-svn: 194792
 2013-11-15 08:07:34 +00:00
Vladimir Medic
97a94dc2fb Fix bug in .gpword directive parsing. 
llvm-svn: 194570
 2013-11-13 13:18:04 +00:00
Zoran Jovanovic
feadcc01d7 Support for microMIPS trap instruction with immediate operands. 
llvm-svn: 194569
 2013-11-13 13:15:03 +00:00
Vladimir Medic
841be82cec This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand. 
llvm-svn: 194562
 2013-11-13 09:48:53 +00:00
Zoran Jovanovic
291725e9c0 Test for microMIPS trap instructions. 
llvm-svn: 194258
 2013-11-08 14:55:31 +00:00
Matheus Almeida
bf40669589 [mips][msa] Update encoding of LDI instruction. 
The encoding was updated in MSA r1.07.

llvm-svn: 194255
 2013-11-08 10:43:11 +00:00
Vladimir Medic
fac4b6d8bf Implement gpword directive for mips, test case added. Stype changes using clang-format are also included. 
llvm-svn: 194145
 2013-11-06 11:27:05 +00:00
Zoran Jovanovic
134add2b71 Support for microMIPS branch instructions. 
llvm-svn: 193992
 2013-11-04 14:53:22 +00:00
Zoran Jovanovic
929213f2ec Support for microMIPS jump instructions 
llvm-svn: 193623
 2013-10-29 16:38:59 +00:00
Zoran Jovanovic
f202867d24 Added tests for microMIPS relocations 1. 
llvm-svn: 193332
 2013-10-24 10:55:00 +00:00
Matheus Almeida
5cc3614e90 [mips][msa] Direct Object Emission support for the LSA instruction. 
llvm-svn: 193240
 2013-10-23 13:20:07 +00:00
Matheus Almeida
06be00bac8 [mips][msa] Direct Object Emission support for conditional branches. 
These branches have a 16-bit offset (R_MIPS_PC16).

List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v

llvm-svn: 193157
 2013-10-22 09:43:32 +00:00
Matheus Almeida
8cdecf1482 [mips][msa] Direct Object Emission support for LD/ST instructions. 
llvm-svn: 193082
 2013-10-21 13:07:13 +00:00
Matheus Almeida
49a9f349f1 [mips][msa] Direct Object Emission support for LDI instructions. 
llvm-svn: 193081
 2013-10-21 12:56:20 +00:00
Matheus Almeida
c0cc50e68b [mips][msa] Direct Object Emission support for MOVE.v. 
llvm-svn: 193080
 2013-10-21 12:43:54 +00:00
Matheus Almeida
e54e855dbb [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. 
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon 
as GAS starts accepting them by name as that would make the assembly easier to read.

llvm-svn: 193078
 2013-10-21 12:26:50 +00:00
Matheus Almeida
1fede43958 [mips][msa] Direct Object Emission of SPLAT instruction. 
llvm-svn: 193077
 2013-10-21 12:07:26 +00:00
Matheus Almeida
1760b2c642 [mips][msa] Fix definition of SLD instruction. 
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.

llvm-svn: 193076
 2013-10-21 11:47:56 +00:00
Akira Hatanaka
d3a40c1178 [mips] Set HI/LO registers' HWEncoding field. 
llvm-svn: 192661
 2013-10-15 01:00:00 +00:00
Matheus Almeida
ddef49ec19 [mips][msa] Direct Object Emission support for BIT instructions. 
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}

llvm-svn: 192589
 2013-10-14 13:07:39 +00:00
Matheus Almeida
7f2a89252c [mips][msa] Direct Object Emission support for VEC instructions. 
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.

llvm-svn: 192588
 2013-10-14 12:57:18 +00:00
Matheus Almeida
8228438976 [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. 
llvm-svn: 192587
 2013-10-14 12:38:17 +00:00
Matheus Almeida
20c2576009 [mips][msa] Direct Object Emission for the majority of the ELM instructions. 
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}

llvm-svn: 192586
 2013-10-14 12:22:43 +00:00
Matheus Almeida
467e191e55 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. 
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.

llvm-svn: 192582
 2013-10-14 11:49:30 +00:00
Matheus Almeida
c2695f53f2 This reverts 192447 because of compiler warning generated on darwin build. 
llvm-svn: 192451
 2013-10-11 13:58:32 +00:00
Matheus Almeida
ee726b70e1 This reverts r192449 because of compiler warning generated on darwin build. 
llvm-svn: 192450
 2013-10-11 13:56:12 +00:00
Matheus Almeida
394228ce3f [mips][msa] Direct Object Emission for the majority of the ELM instructions. 
llvm-svn: 192449
 2013-10-11 13:39:49 +00:00
Matheus Almeida
4a18a3f38a [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. 
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.

llvm-svn: 192447
 2013-10-11 13:29:36 +00:00