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13910 Commits

Author SHA1 Message Date
Evan Cheng
ec4cc9ce14 Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity. 
llvm-svn: 102237
 2010-04-24 04:44:57 +00:00
Dan Gohman
6a48222bd8 Change TargetData's algorithm for computing defualt vector type 
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.

llvm-svn: 102206
 2010-04-23 19:41:15 +00:00
Stuart Hastings
ad81819149 Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
llvm-svn: 102199
 2010-04-23 19:03:32 +00:00
Evan Cheng
9228d598ad Fix X86ISD::CMP i16 to i32 promotion. 
llvm-svn: 102192
 2010-04-23 18:21:16 +00:00
Jim Grosbach
b9dccb6103 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.

llvm-svn: 102144
 2010-04-22 23:24:18 +00:00
Dan Gohman
d819e7fc95 Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel 
and into SelectionDAGBuilder and FastISel.

llvm-svn: 102123
 2010-04-22 20:46:50 +00:00
Evan Cheng
da832d5c85 - It's not safe to promote rotates (at least not trivially). 
- Some code refactoring.

llvm-svn: 102111
 2010-04-22 20:19:46 +00:00
Johnny Chen
c23127cb7e Modified some assert() msg strings; no other functionality change. 
llvm-svn: 102008
 2010-04-21 18:37:48 +00:00
Evan Cheng
dbfb7dc438 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181

llvm-svn: 101984
 2010-04-21 03:18:23 +00:00
Evan Cheng
0f4671b0dd isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 
llvm-svn: 101979
 2010-04-21 01:47:12 +00:00
Evan Cheng
e67a37c4ce Trim include. 
llvm-svn: 101978
 2010-04-21 01:39:06 +00:00
Dan Gohman
4ff2d817a3 Add more const qualifiers on TargetMachine and friends. 
llvm-svn: 101977
 2010-04-21 01:34:56 +00:00
Johnny Chen
6e4b1607ee Thumb instructions which have reglist operands at the end and predicate operands 
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.

llvm-svn: 101974
 2010-04-21 01:01:19 +00:00
Bill Wendling
9bf4b878e0 Handle a displacement location in 64-bit as an RIP-relative displacement. It 
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:

target triple = "x86_64-apple-darwin"

define double @func(double %a) {
  %tmp1 = fmul double %a, 5.000000e-01            ; <double> [#uses=1]
  ret double %tmp1
}

define i32 @main() nounwind {
  %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
  ret i32 0
}

llvm-svn: 101965
 2010-04-21 00:34:04 +00:00
Chris Lattner
6db0f451a7 teach the x86 address matching stuff to handle 
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

llvm-svn: 101958
 2010-04-20 23:18:40 +00:00
Dale Johannesen
510282d54b Because of the EMMS problem, right now we have to support 
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own.  This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)

llvm-svn: 101951
 2010-04-20 22:34:09 +00:00
Johnny Chen
d7ffae797f Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error), 
instead of just asserting.

llvm-svn: 101942
 2010-04-20 21:29:28 +00:00
Johnny Chen
bd5bf58029 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', 
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915
 2010-04-20 17:28:50 +00:00
Chris Lattner
04fb51984f teach cellspu how to return i8 and i16 from calls, 
patch by Kalle Raiskila!

llvm-svn: 101875
 2010-04-20 05:36:09 +00:00
Chris Lattner
339a3cd59b disable optimizations in this directory for MSVC9. This avoids 
an optimizer infinite loop on the file, PR6866.

llvm-svn: 101854
 2010-04-20 01:11:32 +00:00
Johnny Chen
4f388a02d6 Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where 
d==15 is considered illegal.  Return false instead of assert().

llvm-svn: 101852
 2010-04-20 01:01:57 +00:00
Eric Christopher
53e7e0fcfb Remove the palignr intrinsics now that we lower them to vector shuffles, 
shifts and null vectors. Autoupgrade these to what we'd lower them to.

Add a testcase to exercise this.

llvm-svn: 101851
 2010-04-20 00:59:54 +00:00
Johnny Chen
1b36569ba8 More IT instruction error-handling improvements from fuzzing. 
llvm-svn: 101839
 2010-04-20 00:15:41 +00:00
Johnny Chen
2d0dca9099 Better error handling of invalid IT mask '0000', instead of just asserting. 
llvm-svn: 101827
 2010-04-19 23:02:58 +00:00
Dan Gohman
45789ce594 Delete an unnecessary reference to SelectionDAGISel::BB. 
llvm-svn: 101824
 2010-04-19 22:48:45 +00:00
Johnny Chen
fe24cdbba8 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.

llvm-svn: 101817
 2010-04-19 21:19:52 +00:00
Evan Cheng
8efe9e0351 More progress on promoting i16 operations to i32 for x86. Work in progress. 
llvm-svn: 101808
 2010-04-19 19:29:22 +00:00
Johnny Chen
b386de1758 Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand 
instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)
llvm-svn: 101788
 2010-04-19 17:16:40 +00:00
Johnny Chen
091c01cb2f ARM disassembler did not react to recent changes to the NEON instruction table. 
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.

llvm-svn: 101784
 2010-04-19 16:20:34 +00:00
Anton Korobeynikov
dc153b7539 Add missed part of prev. commit 
llvm-svn: 101755
 2010-04-18 20:41:42 +00:00
Anton Korobeynikov
e325c693a5 Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
 2010-04-18 20:31:01 +00:00
Chris Lattner
99d17acb35 fix PR6332, allowing an index of zero into a zero sized array 
even if the element of the array has no size.

llvm-svn: 101662
 2010-04-17 19:02:33 +00:00
Chris Lattner
65d1e40895 teach the x86 asm parser how to handle segment prefixes 
in memory operands.  rdar://7874844

llvm-svn: 101661
 2010-04-17 18:56:34 +00:00
Dan Gohman
fba34ef042 Fix -Wcast-qual warnings. 
llvm-svn: 101655
 2010-04-17 17:42:52 +00:00
Chris Lattner
99878c7ca4 remove a dead variable, PR6856 
llvm-svn: 101648
 2010-04-17 17:28:00 +00:00
Dan Gohman
3dde4fe35f Add const qualifiers to TargetLoweringObjectFile usage. 
llvm-svn: 101640
 2010-04-17 16:44:48 +00:00
Dan Gohman
b5109cda0e Use const_cast instead of a C-style cast to cast away const. 
llvm-svn: 101639
 2010-04-17 16:43:55 +00:00
Dan Gohman
6065ff317b Delete now-unnecessary const_casts. 
llvm-svn: 101637
 2010-04-17 15:32:28 +00:00
Dan Gohman
87af9f6bf4 Use cast instead of dyn_cast when assuming success. 
llvm-svn: 101636
 2010-04-17 15:31:16 +00:00
Dan Gohman
a0f855157e Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
 2010-04-17 15:26:15 +00:00
Dan Gohman
5c8db5ab3f Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.

llvm-svn: 101634
 2010-04-17 14:41:14 +00:00
Chandler Carruth
c03e85229d Name these stub files consistently with the SPU and PPC targets' conventions. 
Also rename the classes appropriately. The CMake build already used these
names.

llvm-svn: 101631
 2010-04-17 08:50:29 +00:00
Chris Lattner
42337931b2 a bunch of ssse3 instructions are misencoded to think they have an 
i8 field when they really do not.  This fixes rdar://7840289

llvm-svn: 101629
 2010-04-17 07:38:24 +00:00
Evan Cheng
6442d111dd More work to allow dag combiner to promote 16-bit ops to 32-bit. 
llvm-svn: 101621
 2010-04-17 06:13:15 +00:00
Bob Wilson
7e53f886d2 Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this 
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.

llvm-svn: 101615
 2010-04-17 05:30:19 +00:00
Chris Lattner
136547652d add a note 
llvm-svn: 101581
 2010-04-16 23:52:30 +00:00
Eric Christopher
e78496e5f1 Revert 101465, it broke internal OpenGL testing. 
Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.

llvm-svn: 101579
 2010-04-16 23:37:20 +00:00
Johnny Chen
8de98d4036 Cast to (uint64_t) instead of relying on the "ul" suffix. 
llvm-svn: 101573
 2010-04-16 23:30:28 +00:00
Dan Gohman
982923742d Add skeleton target-specific SelectionDAGInfo files. 
llvm-svn: 101564
 2010-04-16 23:04:22 +00:00
Johnny Chen
2b1390e9bc Fixed logic error. Should check Builder for validity before calling SetSession 
on it.

llvm-svn: 101563
 2010-04-16 23:02:25 +00:00