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Commit Graph

286 Commits

Author SHA1 Message Date
Chris Lattner
9e5cc35593 Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464
2007-12-30 23:10:15 +00:00
Chris Lattner
7504adbd72 More cleanups for MachineOperand:
- Eliminate the static "print" method for operands, moving it
    into MachineOperand::print.
  - Change various set* methods for register flags to take a bool
    for the value to set it to.  Remove unset* methods.
  - Group methods more logically by operand flavor in MachineOperand.h

llvm-svn: 45461
2007-12-30 21:56:09 +00:00
Chris Lattner
4d0361fbf2 Shrinkify the machine operand creation method names.
llvm-svn: 45433
2007-12-30 00:45:46 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng
1d95b669b6 Make better use of instructions that clear high bits; fix various 2-wide shuffle bugs.
llvm-svn: 45058
2007-12-15 03:00:47 +00:00
Evan Cheng
55e450d6eb Actually, MOVPQIto64mr is a dup of MOVPQI2QImr, MOV64toPQIrm is a dup of MOVQI2PQIrm.
llvm-svn: 45041
2007-12-14 20:08:14 +00:00
Nate Begeman
e9067c13ec Allow the JIT to encode MMX instructions
llvm-svn: 44869
2007-12-11 18:06:14 +00:00
Evan Cheng
8464a0bf00 Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.

llvm-svn: 44600
2007-12-05 03:14:33 +00:00
Evan Cheng
58b387dfb0 Remove redundant foldMemoryOperand variants and other code clean up.
llvm-svn: 44517
2007-12-02 08:30:39 +00:00
Evan Cheng
79e8b92dc3 Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
llvm-svn: 44479
2007-12-01 02:07:52 +00:00
Evan Cheng
fd33cb316f Clean up sub-register implementation by moving subReg information back to
MachineOperand auxInfo. Previous clunky implementation uses an external map
to track sub-register uses. That works because register allocator uses
a new virtual register for each spilled use. With interval splitting (coming
soon), we may have multiple uses of the same register some of which are
of using different sub-registers from others. It's too fragile to constantly
update the information.

llvm-svn: 44104
2007-11-14 07:59:08 +00:00
Dale Johannesen
5fd9e7a615 Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.

llvm-svn: 44056
2007-11-13 19:13:01 +00:00
Evan Cheng
994043f515 Fix x86-64 jit: remove reliance on Dwarf numbers.
llvm-svn: 44048
2007-11-13 17:54:34 +00:00
Anton Korobeynikov
8e8473c783 Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
2007-11-11 19:50:10 +00:00
Dale Johannesen
eca19e7eca Revert previous rewrite per chris's comments.
llvm-svn: 43950
2007-11-09 18:07:11 +00:00
Dale Johannesen
8a9ec1582b Rewrite Dwarf number handling per review comments.
llvm-svn: 43918
2007-11-09 00:47:10 +00:00
Dale Johannesen
b11aca8a92 Complete conditionalization of Dwarf reg numbers.
Would somebody not on Darwin please make sure this
doesn't break anything.  Exception handling failures
would be the most likely symptom.

llvm-svn: 43844
2007-11-07 21:48:35 +00:00
Dale Johannesen
a863789700 Interchange Dwarf numbers of ESP and EBP on x86 Darwin.
Much improvement in exception handling.

llvm-svn: 43794
2007-11-07 00:25:05 +00:00
Evan Cheng
c49995c027 Use movups to spill / restore SSE registers on targets where stacks alignment is
less than 16. This is a temporary solution until dynamic stack alignment is
implemented.

llvm-svn: 43703
2007-11-05 07:30:01 +00:00
Anton Korobeynikov
0d3f43480e Fix off-by-one stack offset computations (dwarf information) for callee-saved
registers in case, when FP pointer was eliminated. This should fixes misc. random
EH-related crahses, when stuff is compiled with -fomit-frame-pointer.
Thanks Duncan for nailing this bug!

llvm-svn: 43381
2007-10-26 09:13:24 +00:00
Evan Cheng
ddeab10144 Fix an unfolding bug.
llvm-svn: 43212
2007-10-22 03:03:20 +00:00
Evan Cheng
b56784f9ea Resolve unfold tables ambiguity.
llvm-svn: 43194
2007-10-19 23:50:58 +00:00
Evan Cheng
ded6550885 Local spiller optimization:
Turn a store folding instruction into a load folding instruction. e.g.
     xorl  %edi, %eax
     movl  %eax, -32(%ebp)
     movl  -36(%ebp), %eax
     orl   %eax, -32(%ebp)
=>
     xorl  %edi, %eax
     orl   -36(%ebp), %eax
     mov   %eax, -32(%ebp)
This enables the unfolding optimization for a subsequent instruction which will
also eliminate the newly introduced store instruction.

llvm-svn: 43192
2007-10-19 21:23:22 +00:00
Evan Cheng
0449186690 - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.

llvm-svn: 43153
2007-10-18 22:40:57 +00:00
Evan Cheng
c852780685 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
llvm-svn: 43150
2007-10-18 21:29:24 +00:00
Evan Cheng
2e2d6358bc Change unfoldMemoryOperand(). User is now responsible for passing in the
register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.

llvm-svn: 42946
2007-10-13 02:35:06 +00:00
Evan Cheng
c7b7a3cb74 Fold load / store into MOV32to32_ and MOV16to16_.
llvm-svn: 42895
2007-10-12 08:38:01 +00:00
Arnold Schwaighofer
d47210011e Added tail call optimization to the x86 back end. It can be
enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870
2007-10-11 19:40:01 +00:00
Chris Lattner
fcccf4b6c4 disable this entirely: it is causing use of invalidated iterators and infinite looping.
llvm-svn: 42739
2007-10-07 22:00:31 +00:00
Chris Lattner
39dbb82db2 Fix many regressions on x86 by avoiding dereferencing the end iterator.
llvm-svn: 42738
2007-10-07 21:53:12 +00:00
Anton Korobeynikov
54ecd77023 Oops, I really wanted to commit this part also :)
llvm-svn: 42700
2007-10-06 16:39:43 +00:00
Anton Korobeynikov
34fefcf678 Move merge code into new helper function.
llvm-svn: 42699
2007-10-06 16:17:49 +00:00
Evan Cheng
6e5205d379 Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's.
llvm-svn: 42624
2007-10-05 01:34:55 +00:00
Evan Cheng
3537dbbd1e Refactor code to add load / store folded instructions -> register only
instructions reverse map.

llvm-svn: 42509
2007-10-01 23:44:33 +00:00
Evan Cheng
f3c130a8b6 Enabling new condition code modeling scheme.
llvm-svn: 42459
2007-09-29 00:00:36 +00:00
Dan Gohman
50747737a5 TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.

llvm-svn: 42419
2007-09-27 23:12:31 +00:00
Evan Cheng
d8ab90ae1f Use GR64 in 64-bit mode.
llvm-svn: 42417
2007-09-27 21:50:05 +00:00
Evan Cheng
0f9e307353 - Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from).
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.

llvm-svn: 42372
2007-09-26 21:31:07 +00:00
Evan Cheng
5f9e291240 Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!

llvm-svn: 42346
2007-09-26 06:25:56 +00:00
Anton Korobeynikov
8cd666b659 Correctly restore stack pointer after realignment in main() on Cygwin/Mingw32
llvm-svn: 42332
2007-09-26 00:13:34 +00:00
Evan Cheng
24c5a1a484 Missing load / store folding entries.
llvm-svn: 42323
2007-09-25 22:10:43 +00:00
Evan Cheng
36b3babfde Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.

llvm-svn: 42285
2007-09-25 01:57:46 +00:00
Dan Gohman
32b1df2aa3 The code that used the StartLabelId label was removed, so remove the
code that creates the label too.

llvm-svn: 42265
2007-09-24 16:44:26 +00:00
Dan Gohman
eb622df2ef Fix several more entries in the x86 reload/remat folding tables.
llvm-svn: 42162
2007-09-20 14:17:21 +00:00
Evan Cheng
ec83699473 PSHUFDmi, etc. are actually folding a load, not a store.
llvm-svn: 42147
2007-09-19 19:02:47 +00:00
Dan Gohman
be3b005b2d Move the entries for 64-bit CMP, IMUL, and a few others into the correct
tables so that they are eligible for reload/remat folding. And add
entries for JMP and CALL.

llvm-svn: 42094
2007-09-18 14:59:14 +00:00
Dale Johannesen
46adce144c Remove RSTRegClass case from loadRegFromStackSlot
and storeRegToStackSlot.  Evan and I concluded this
should never be needed and it appears to be true.
(It if is needed, adjustment would be needed for
long double to work.)

llvm-svn: 42049
2007-09-17 20:15:38 +00:00
Dale Johannesen
575bd6070a Remove the assumption that FP's are either float or
double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).

llvm-svn: 41967
2007-09-14 22:26:36 +00:00
Dan Gohman
fb60c0dfed Remove isReg, isImm, and isMBB, and change all their users to use
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958
2007-09-14 20:33:02 +00:00
Evan Cheng
4715ccb29c It's not safe to rematerialize MOV32r0 etc. by simply cloning the original
instruction. These are implemented with xor which will modify the conditional
code. They should be rematerialized as move instructions.

llvm-svn: 41802
2007-09-10 20:48:53 +00:00