Chad Rosier
8af97606a9
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
...
load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
Evan Cheng
1acd685d87
Add bundle aware API for querying instruction properties and switch the code
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generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Chad Rosier
70dd1f98af
[arm-fast-isel] Doublewords only require word-alignment.
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rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
Bob Wilson
f054e82281
Fix 80-column issues.
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llvm-svn: 145783
2011-12-04 00:52:23 +00:00
Chad Rosier
d1968c9ed6
[arm-fast-isel] Unaligned stores of floats require special care.
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rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
Nick Lewycky
7d0d3c2d58
Move global variables in TargetMachine into new TargetOptions class. As an API
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change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
Chad Rosier
b3b2871bbf
[arm-fast-isel] After promoting a function parameter be sure to update the
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argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
Duncan Sands
ec13954efd
Silence wrong warnings from GCC about variables possibly being used
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uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.
llvm-svn: 145239
2011-11-28 10:31:27 +00:00
Chad Rosier
70dab03f8e
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
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llvm-svn: 144959
2011-11-18 01:17:34 +00:00
Chad Rosier
7d2af13ccb
Add TODO comment.
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llvm-svn: 144920
2011-11-17 21:46:13 +00:00
Chad Rosier
47928b03f3
Dead code.
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llvm-svn: 144888
2011-11-17 07:24:49 +00:00
Chad Rosier
c9ed1d9072
Don't unconditionally set the kill flag.
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rdar://10456186
llvm-svn: 144872
2011-11-17 01:16:53 +00:00
Chad Rosier
69f9c432a6
Check to make sure we can select the instruction before trying to put the
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operands into a register. Otherwise, we may materialize dead code.
llvm-svn: 144805
2011-11-16 18:39:44 +00:00
Chad Rosier
17577c9394
Add FIXME comment.
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llvm-svn: 144743
2011-11-16 00:32:20 +00:00
Jay Foad
7d05fea7f8
Remove some unnecessary includes of PseudoSourceValue.h.
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llvm-svn: 144631
2011-11-15 07:24:32 +00:00
Chad Rosier
4e05d7f12c
Supporting inline memmove isn't going to be worthwhile. The only way to avoid
...
violating a dependency is to emit all loads prior to stores. This would likely
cause a great deal of spillage offsetting any potential gains.
llvm-svn: 144585
2011-11-14 23:04:09 +00:00
Chad Rosier
48b92815e0
Add support for inlining small memcpys.
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rdar://10412592
llvm-svn: 144578
2011-11-14 22:46:17 +00:00
Chad Rosier
8aa8f14940
Fix a performance regression from r144565. Positive offsets were being lowered
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into registers, rather then encoded directly in the load/store.
llvm-svn: 144576
2011-11-14 22:34:48 +00:00
Chad Rosier
65395ac4d0
Add support for Thumb load/stores with negative offsets.
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rdar://10412592
llvm-svn: 144565
2011-11-14 20:22:27 +00:00
Chad Rosier
0e5094ca87
Add support for ARM halfword load/stores and signed byte loads with negative
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offsets.
rdar://10412592
llvm-svn: 144518
2011-11-14 04:09:28 +00:00
Chad Rosier
58ab241006
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
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llvm-svn: 144494
2011-11-13 09:44:21 +00:00
Chad Rosier
8cfccc356e
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
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llvm-svn: 144492
2011-11-13 05:14:43 +00:00
Chad Rosier
0770c4834a
Fix comments.
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llvm-svn: 144490
2011-11-13 04:25:02 +00:00
Chad Rosier
acd199b5a4
Add support for emitting both signed- and zero-extend loads. Fix
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SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
Chad Rosier
a2a0fbeded
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
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llvm-svn: 144426
2011-11-11 23:31:03 +00:00
Chad Rosier
98f48b009e
Rename variables to avoid confusion. No functionallity change intended.
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llvm-svn: 144377
2011-11-11 06:27:41 +00:00
Chad Rosier
feb72bfc08
Add support for using immediates with select instructions.
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rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
Chad Rosier
38f07d3f9c
When loading a value, treat an i1 as an i8.
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llvm-svn: 144356
2011-11-11 02:38:59 +00:00
Chad Rosier
ac92994773
Add support for using MVN to materialize negative constants.
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rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
Chad Rosier
7b7dced006
When in ARM mode, LDRH/STRH require special handling of negative offsets.
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For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
Chad Rosier
69cdae5eb9
For immediate encodings of icmp, zero or sign extend first. Then
...
determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
Chad Rosier
f47b941510
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
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rdar://10418009
llvm-svn: 144213
2011-11-09 21:30:12 +00:00
Chad Rosier
e32fed6868
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
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remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
Chad Rosier
24a6e399f8
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
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No functional change intended.
llvm-svn: 144122
2011-11-08 21:12:00 +00:00
Chad Rosier
4b12a5b7fc
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
...
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
llvm-svn: 144047
2011-11-08 00:03:32 +00:00
Chad Rosier
806ffd8918
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
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zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
llvm-svn: 143821
2011-11-05 20:16:15 +00:00
Chad Rosier
5e54485e51
Cannot create a result register for non-legal types.
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llvm-svn: 143749
2011-11-04 23:45:39 +00:00
Chad Rosier
a900a3e2f6
When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit
...
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend. This prevents us from materializing things
such as 'true' (i.e., i1 1).
llvm-svn: 143743
2011-11-04 23:09:49 +00:00
Chad Rosier
0143eb6f22
Enable support for materializing i1, i8, and i16 integers via move immediate.
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llvm-svn: 143739
2011-11-04 22:29:00 +00:00
Chad Rosier
8836fe3bbd
Indentation.
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llvm-svn: 143670
2011-11-04 00:58:10 +00:00
Chad Rosier
21cd759234
Add fast-isel support for returning i1, i8, and i16.
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llvm-svn: 143669
2011-11-04 00:50:21 +00:00
Chad Rosier
74c4e2c2d9
Add support for sign-extending non-legal types in SelectSIToFP().
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llvm-svn: 143603
2011-11-03 02:04:59 +00:00
Chad Rosier
8a613c5ec5
Add support for comparing integer non-legal types.
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llvm-svn: 143559
2011-11-02 18:08:25 +00:00
Chad Rosier
e94ff7c26e
Factor out an EmitIntExt function. No functionality change intended.
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llvm-svn: 143547
2011-11-02 17:20:24 +00:00
Chad Rosier
f72870096b
Factor out a SelectTrunc function. No functionality change intended.
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llvm-svn: 143523
2011-11-02 00:18:48 +00:00
Chad Rosier
e76ba1b654
A branch predicated on a constant can just FastEmit an unconditional branch.
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llvm-svn: 143086
2011-10-27 00:21:16 +00:00
Chad Rosier
e3141f4f8b
Add a TODO comment. FastISel works by parsing each basic block from the bottom
...
up. Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle. This creates many more
opportunities for target specific fast-isel.
llvm-svn: 143079
2011-10-26 23:34:37 +00:00
Chad Rosier
75378507e3
Factor a little more code into EmitCmp, which should have been done in the first
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place. No functional change intended.
llvm-svn: 143078
2011-10-26 23:25:44 +00:00
Chad Rosier
52109646da
Use EmitCmp in SelectBranch. No functional change intended.
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llvm-svn: 143076
2011-10-26 23:17:28 +00:00
Chad Rosier
3f38cb48de
Factor out an EmitCmp function that can be used by both SelectCmp and
...
SelectBranch. No functional change intended.
llvm-svn: 143072
2011-10-26 22:47:55 +00:00