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Commit Graph

31613 Commits

Author SHA1 Message Date
Reid Kleckner
9f52049132 x86: Fix large model calls to __chkstk for dynamic allocas
In the large code model, we now put __chkstk in %r11 before calling it.

Refactor the code so that we only do this once. Simplify things by using
__chkstk_ms instead of __chkstk on cygming. We already use that symbol
in the prolog emission, and it simplifies our logic.

Second half of PR18582.

llvm-svn: 227519
2015-01-29 23:58:04 +00:00
Eric Christopher
52da93dd7a Remove unnecessary calls to getSubtarget/getSubtargetImpl from the
MSP430 backend.

llvm-svn: 227517
2015-01-29 23:46:42 +00:00
Eric Christopher
6353559d63 Remove unused header.
llvm-svn: 227516
2015-01-29 23:46:39 +00:00
Sanjay Patel
b1fd7a88a4 Change SmallVector param to the more general ArrayRef; NFCI
llvm-svn: 227514
2015-01-29 23:35:04 +00:00
Eric Christopher
ce8b9be5fd Get rid of a few calls through the subtarget to get the ABI
that's actually sitting on the target machine.

llvm-svn: 227513
2015-01-29 23:27:45 +00:00
Eric Christopher
faf4f71040 Remove most of the TargetMachine::getSubtarget/getSubtargetImpl
calls that don't take a Function argument from Mips. Notable
exceptions: the AsmPrinter and MipsTargetObjectFile. The
latter needs to be fixed, and the former will be fixed when the
general AsmPrinter changes happen.

llvm-svn: 227512
2015-01-29 23:27:36 +00:00
Reid Kleckner
d0ab1ab0a3 x86: Remove the W64ALLOCA pseudo
This is just an alias for CALL64pcrel32, and we can just use that opcode
with explicit defs in the MI.

No functionality change.

llvm-svn: 227508
2015-01-29 23:09:37 +00:00
Chad Rosier
27f06713e9 [AArch64] Add INITIALIZE_PASS macros to AArch64A57FPLoadBalancing.
These are needed so this pass will produce output when
e.g. -print-after-all is used.

Phabricator Review: http://reviews.llvm.org/D7264
Patch by Geoff Berry <gberry@codeaurora.org>!

llvm-svn: 227506
2015-01-29 22:57:37 +00:00
Reid Kleckner
d9129cb1d5 Update comments to use unreachable instead of llvm.trap, as implemented now
win64: Call __chkstk through a register with the large code model

Fixes half of PR18582. True dynamic allocas will still have a
CALL64pcrel32 which will fail.

Reviewers: majnemer

Differential Revision: http://reviews.llvm.org/D7267

llvm-svn: 227503
2015-01-29 22:33:00 +00:00
Colin LeMahieu
54b41eed7b [Hexagon] Organizing tests and adding a few missing jump instruction encodings.
llvm-svn: 227498
2015-01-29 21:47:15 +00:00
Colin LeMahieu
13519e2bd4 [Hexagon] Adding missing instruction encodings and tests.
llvm-svn: 227495
2015-01-29 21:30:22 +00:00
Colin LeMahieu
d1253ac69a [Hexagon] Adding alu vector instructions
llvm-svn: 227493
2015-01-29 21:09:30 +00:00
David Blaikie
ab3f1389ea Matching ARM change for r227481: DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps.
llvm-svn: 227488
2015-01-29 20:23:47 +00:00
Matt Arsenault
97c228de40 R600/SI: Implement enableAggressiveFMAFusion
Add tests for the various combines. This should
always be at least cycle neutral on all subtargets for f64,
and faster on some. For f32 we should prefer selecting
v_mad_f32 over v_fma_f32.

llvm-svn: 227484
2015-01-29 19:34:32 +00:00
Matt Arsenault
2c9174cd90 R600/SI: Add subtarget feature for if f32 fma is fast
llvm-svn: 227483
2015-01-29 19:34:25 +00:00
Matt Arsenault
20beceb945 R600/SI: Fix tonga's basic scheduling model
llvm-svn: 227482
2015-01-29 19:34:18 +00:00
David Blaikie
effa0911ff DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps
The use of the DbgLoc in FastISel is probably something we should fix.
It's prone to leaking the wrong location into instructions - we should
have a clear chain of custody from the debug location of an IR
Instruction to that of a MachineInstr to avoid such leakage.

llvm-svn: 227481
2015-01-29 19:09:18 +00:00
Rafael Espindola
16f3006ec0 Compute the ELF SectionKind from the flags.
Any code creating an MCSectionELF knows ELF and already provides the flags.

SectionKind is an abstraction used by common code that uses a plain
MCSection.

Use the flags to compute the SectionKind. This removes a lot of
guessing and boilerplate from the MCSectionELF construction.

llvm-svn: 227476
2015-01-29 17:33:21 +00:00
Colin LeMahieu
60586de39c [Hexagon] Deleting old variants of intrinsics and adding missing tests.
llvm-svn: 227474
2015-01-29 17:26:56 +00:00
Colin LeMahieu
f319d92955 [Hexagon] Adding CR intrinsic tests.
llvm-svn: 227463
2015-01-29 16:55:37 +00:00
Tom Stellard
6ae0912446 R600/SI: Remove stray debug statements
llvm-svn: 227462
2015-01-29 16:55:28 +00:00
Tom Stellard
33ad0a78c5 R600/SI: Define a schedule model and enable the generic machine scheduler
The schedule model is not complete yet, and could be improved.

llvm-svn: 227461
2015-01-29 16:55:25 +00:00
Colin LeMahieu
28811bcf4c [Hexagon] Deleting unused classes.
llvm-svn: 227460
2015-01-29 16:35:38 +00:00
Robert Lougher
f135e638ae [X86] Use single add/sub for large stack offsets
For large stack offsets the compiler generates multiple immediate mode
sub/add instructions in the prologue/epilogue.  This patch makes the
compiler place the final amount to be added/subtracted into a register,
which is then added/substracted with a single operation.

Differential Revision: http://reviews.llvm.org/D7226

llvm-svn: 227458
2015-01-29 16:18:29 +00:00
Colin LeMahieu
332a5243a2 [Hexagon] Adding XTYPE/PRED intrinsic tests. Converting predicate types to i32 instead of i1.
llvm-svn: 227457
2015-01-29 16:08:43 +00:00
Bill Schmidt
f10debced6 [PowerPC] Complete setting the baseline for ppc64le
Patch by Nemanja Ivanovic.

As was uncovered by the failing test case (when run on non-PPC
platforms), the feature set when compiling with -march=ppc64le was not
being picked up. This change ensures that if the -mcpu option is not
specified, the correct feature set is picked up regardless of whether
we are on PPC or not.

llvm-svn: 227455
2015-01-29 15:59:09 +00:00
Rafael Espindola
4fcf322f90 Remove MergeableConst.
Only the specific ones (MergeableConst4, MergeableConst8, MergeableConst16) are
handled specially.

llvm-svn: 227440
2015-01-29 14:12:41 +00:00
Vladimir Medic
96ce968d89 [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
llvm-svn: 227430
2015-01-29 11:33:41 +00:00
Eric Christopher
fac1441f08 Remove getSubtargetImpl from AArch64ISelLowering and cache the
correct subtarget by passing it in during the constructor as
TargetLowering is Subtarget specific.

llvm-svn: 227402
2015-01-29 00:19:42 +00:00
Eric Christopher
b162d40442 Remove getSubtargetImpl from ARMISelLowering and cache the
correct subtarget by passing it in during the constructor as
TargetLowering is Subtarget specific.

llvm-svn: 227401
2015-01-29 00:19:39 +00:00
Eric Christopher
c8b4431ff7 Small cleanup in ARMFastISel initialization.
llvm-svn: 227400
2015-01-29 00:19:37 +00:00
Eric Christopher
1e7b535a5c Migrate ARM except for TTI, AsmPrinter, and frame lowering
away from getSubtargetImpl.

llvm-svn: 227399
2015-01-29 00:19:33 +00:00
Sanjay Patel
9f981f73d6 fix typos; NFC
llvm-svn: 227386
2015-01-28 22:37:32 +00:00
Colin LeMahieu
f323a70677 [Hexagon] Updating several V5 intrinsics and adding FP tests.
llvm-svn: 227379
2015-01-28 22:08:16 +00:00
Simon Pilgrim
b7a5ea632e Spelling fixes. NFC.
llvm-svn: 227376
2015-01-28 22:03:52 +00:00
Simon Pilgrim
60ccce57a6 Line endings fix. NFC.
llvm-svn: 227374
2015-01-28 21:56:52 +00:00
Zoran Jovanovic
9b40c3c637 [mips][microMIPS] Implement SWM and LWM aliases
Differential Revision: http://reviews.llvm.org/D5820

llvm-svn: 227373
2015-01-28 21:52:27 +00:00
Sanjay Patel
29a4096408 invert check for less indentation; use local vars to reduce duplication; NFC
llvm-svn: 227355
2015-01-28 19:44:21 +00:00
Colin LeMahieu
e461a384f0 [Hexagon] Updating many V4 intrinsic patterns. Adding missing instruction and deleting unused classes.
llvm-svn: 227353
2015-01-28 19:39:09 +00:00
Colin LeMahieu
629196ef3e [Hexagon] Adding XTYPE/MPY intrinsic tests and some missing multiply instructions.
llvm-svn: 227347
2015-01-28 19:16:17 +00:00
Colin LeMahieu
159f2e1618 [Hexagon] Deleting a lot of old variants of intrinsics and updating references.
llvm-svn: 227338
2015-01-28 18:29:11 +00:00
Colin LeMahieu
123b7d1e5a [Hexagon] Converting XTYPE/BIT intrinsic patterns and adding tests.
llvm-svn: 227335
2015-01-28 18:06:23 +00:00
Sanjay Patel
f6c1ab1da5 use SDValue methods directly instead of getNode()->* ; NFCI
llvm-svn: 227334
2015-01-28 18:01:31 +00:00
Colin LeMahieu
13e9276fa8 [Hexagon] Replacing XTYPE/SHIFT intrinsic patternss. Adding tests and missing instructions with tests.
llvm-svn: 227330
2015-01-28 17:37:59 +00:00
Jozef Kolek
e6b6be169a [mips][microMIPS] Implement LWGP instruction
Differential Revision: http://reviews.llvm.org/D6650

llvm-svn: 227325
2015-01-28 17:27:26 +00:00
Colin LeMahieu
d39a45731a [Hexagon] Replacing intrinsics for halfword adds and max/min word/dword.
llvm-svn: 227322
2015-01-28 17:06:40 +00:00
Michael Kuperstein
7669714361 [x32] Change the condition from bitness to LP64 for TCRETURNdi64.
TCRETURNmi64, which was mistakenly changed in r227307 will wait for another day.

llvm-svn: 227317
2015-01-28 16:11:35 +00:00
Tom Stellard
4758e65ded R600: Move DataLayout to AMDGPUTargetMachine
This is a follow up to r227113.

It is now required to use the amdgcn target for SI and newer GPUs.

llvm-svn: 227316
2015-01-28 16:04:26 +00:00
Tom Stellard
11f7c6e2bc R600: Use a Southern Islands GPU as the default for the amdgcn target
llvm-svn: 227314
2015-01-28 15:38:42 +00:00
Michael Kuperstein
139e0bbb66 [X86] Reduce some 32-bit imuls into lea + shl
Reduce integer multiplication by a constant of the form k*2^c, where k is in {3,5,9} into a lea + shl. Previously it was only done for imulq on 64-bit platforms, but it makes sense for imull and 32-bit as well.

Differential Revision: http://reviews.llvm.org/D7196

llvm-svn: 227308
2015-01-28 14:08:22 +00:00