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Commit Graph

208040 Commits

Author SHA1 Message Date
Tim Northover
0fd5aa6df8 UBSAN: emit distinctive traps
Sometimes people get minimal crash reports after a UBSAN incident. This change
tags each trap with an integer representing the kind of failure encountered,
which can aid in tracking down the root cause of the problem.
2020-12-08 10:28:26 +00:00
Stefan Gränitz
30acd5d783 [Orc] Two small fixes in TPCDynamicLibrarySearchGenerator
There is one result per lookup symbol, so we have to advance the result iterator no matter whether it's NULL or not.
MissingSymbols variable is unused.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D91707
2020-12-08 10:58:20 +01:00
Stefan Gränitz
6bed7ec3c4 [JITLink][ELF] Route objects to their matching linker backends based on header info
Distinguish objects by target properties address size, endian and machine architecture. So far we only
support x86-64 (ELFCLASS64, ELFDATA2LSB, EM_X86_64).

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D90860
2020-12-08 10:56:01 +01:00
Evgeniy Brevnov
816ffc867c [DSE][NFC] Need to be carefull mixing signed and unsigned types
Currently in some places we use signed type to represent size of an access and put explicit casts from unsigned to signed.
For example: int64_t EarlierSize = int64_t(Loc.Size.getValue());

Even though it doesn't loos bits (immidiatly) it may overflow and we end up with negative size. Potentially that cause later code to work incorrectly. A simple expample is a check that size is not negative.

I think it would be safer and clearer if we use unsigned type for the size and handle it appropriately.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D92648
2020-12-08 16:53:37 +07:00
Anton Afanasyev
0b6954f2b2 [SLP][Test] Differentiate SSE/AVX512 test coverage (NFC)
Add test coverage for SSE/AVX512 for insert-after-bundle.ll test.
Prepare this test for accurate showing of PR46983 fix.
2020-12-08 12:00:52 +03:00
David Blaikie
6c4f0d2a83 Fix shtest-timeout test harder
Don't produce or expect any output from the infinite looping test -
doing so is a recipe for racey flakyness without a longer timeout to
ensure the output is received first, even though that doesn't seem
integral/important to the test. Instead have a plain, no output infinite
loop and check that that is caught and handled.

If for some reason the output is valuable for test coverage - the
timeout should be increased from 1 second to give the process time to
output the text, flush, and for that text to be received and buffered
before the test is timed out.
2020-12-08 00:23:33 -08:00
Qiu Chaofan
8a59a780af [NFC] [PowerPC] Move i1-to-fp tests and use script 2020-12-08 15:20:15 +08:00
Arthur Eubanks
5b11c43641 [test] Pin provenance.ll to legacy PM
It doesn't seem right to port -pa-eval just for one test, punting
decision for how to handle this.
2020-12-07 23:08:02 -08:00
Arthur Eubanks
d2ce694ca0 [test] Fix loop-micro-op-buffer-size-t99.ll under NPM
The NPM runs loop passes on loops in forward program order instead of
the legacy PM's reverse program order, causing some debug output to be
in a different order.
2020-12-07 23:06:57 -08:00
wlei
189f7cb2ab [llvm-profgen][NFC] Fix test failure by making unwinder's output deterministic
Don't know why under Sanitizer build(asan/msan/ubsan), the `std::unordered_map<string, ...>`'s output order is reversed, make the regression test failed.

This change creates a workaround by using sorted container to make the output deterministic.

Reviewed By: hoy, wenlei

Differential Revision: https://reviews.llvm.org/D92816
2020-12-07 22:36:25 -08:00
Qiu Chaofan
04fcf5136e [PowerPC] Implement intrinsic for DARN instruction
Instruction darn was introduced in ISA 3.0. It means 'Deliver A Random
Number'. The immediate number L means:

- L=0, the number is 32-bit (higher 32-bits are all-zero)
- L=1, the number is 'conditioned' (processed by hardware to reduce bias)
- L=2, the number is not conditioned, directly from noise source

GCC implements them in three separate intrinsics: __builtin_darn,
__builtin_darn_32 and __builtin_darn_raw. This patch implements the
same intrinsics. And this change also addresses Bugzilla PR39800.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D92465
2020-12-08 14:08:52 +08:00
Arthur Eubanks
eb76587287 [test] Fix Transforms/LoopVersioningLICM under NPM
There were already both legacy and new PM RUN lines.
Also make the NPM RUN line actually match the legacy PM RUN line.
2020-12-07 21:54:38 -08:00
Arthur Eubanks
e1ee7a2a1d [test] Fix Transforms/LoopVectorize under NPM
The -enable-new-pm=1 translation caused loop-vectorize to run on all
functions, then instcombine, rather than all passes on one function then
the next. This caused the output of -debug-only and -print-after to be
interleaved in an unexpected way.
2020-12-07 21:48:21 -08:00
Arthur Eubanks
f278e220fe [test] Fix store_cost.ll under NPM
The NPM processes loops in forward program order, whereas the legacy PM
processes them in reverse program order. No reason to test both PMs
here, so just stick to the NPM.
2020-12-07 21:19:05 -08:00
Arthur Eubanks
fb35bd9d3c [test] Fix widen-iv.ll under NPM
The -loop-flatten legacy pass preserves loop analyses. The legacy PM
will check all passes that preserve loop analyses that they preserve
LCSSA. This implicitly involves running -loop-simplify. The test
shouldn't depend on verify flags being set in order to run
-loop-simplify, so explicitly add it. The new PM ends up not running it
otherwise.
2020-12-07 19:34:31 -08:00
Kai Luo
6887a6b0ee [DAGCombine][PowerPC] Simplify nabs by using legal smin operation
Convert `0 - abs(x)` to `smin (x, -x)` if `smin` is a legal operation.

Verification: https://alive2.llvm.org/ce/z/vpquFR

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D92637
2020-12-08 03:24:07 +00:00
Esme-Yi
9553b86c6a [PowerPC] Correct the bit-width definition for some imm operand in td.
Summary: The imm operands of some instructions are not defined accurately in td.
This is a small patch to correct these definitions.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D91603
2020-12-08 03:20:12 +00:00
Arthur Eubanks
853ad112ab [test] Fix LoopFusion tests under NewPM
The legacy pass depended on -loop-simplify running. The NPM does not
allow for a non-analysis pass to depend on another non-analysis pass.
2020-12-07 17:37:42 -08:00
Jessica Paquette
fded1f02ae [AArch64][GlobalISel] Refactor G_BRCOND selection
`selectCompareBranch` was hard to understand.

Also, it was being needlessly pessimistic with the `ProduceNonFlagSettingCondBr`
case. It assumed that everything in `selectCompareBranch` would emit a TB(N)Z
or C(B)NZ. That's not true; the G_FCMP + G_BRCOND case would never emit those
instructions, and the G_ICMP + G_BRCOND case was capable of emitting an integer
compare + Bcc.

- Refactor `selectCompareBranch` into separate functions based off of what is
feeding the G_BRCOND's condition.

- Move G_BRCOND selection code from `select` to `selectCompareBranch`.

- Remove duplicated constraint code from the code originally in `select`;
  `emitTestBit` already handles that, so no need to constrain twice.

- Factor out the G_FCMP + G_BRCOND case into `selectCompareBranchFedByFCmp`.

- Split the G_ICMP + G_BRCOND case into an optimization function,
`tryOptCompareBranchFedByICmp` and a general selection function,
`selectCompareBranchFedByICmp`.

- Reduce the number of things passed to `tryOptAndIntoCompareBranch`.

- Improve documentation.

- Give some variables more descriptive names.

Other than improving the code generation for functions with
speculative_load_hardening by getting the logic correct, this is NFC.

Differential Revision: https://reviews.llvm.org/D92582
2020-12-07 17:24:23 -08:00
Valentin Churavy
fa8ef60bf6 [VNCoercion] Disallow coercion between different ni addrspaces
I'm not sure if it would be legal by the IR reference to introduce
an addrspacecast here, since the IR reference is a bit vague on
the exact semantics, but at least for our usage of it (and I
suspect for many other's usage) it is not. For us, addrspacecasts
between non-integral address spaces carry frontend information that the
optimizer cannot deduce afterwards in a generic way (though we
have frontend specific passes in our pipline that do propagate
these). In any case, I'm sure nobody is using it this way at
the moment, since it would have introduced inttoptrs, which
are definitely illegal.

Fixes PR38375

Co-authored-by: Keno Fischer <keno@alumni.harvard.edu>

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D50010
2020-12-07 20:19:48 -05:00
Douglas Yung
40bc19958f Fixup test in path to use C:\ instead of D:\ which may be mapped to a removable.
Our internal build bot hit a failure in llvm/test/tools/llvm-symbolizer/pdb/missing_pdb.test
because the test was checking for an error message that is emitted when a pdb file is
missing. But when the drive is mapped to a removalable drive (such as a DVD drive) in
Windows, you get a different error message which causes the test to fail.

This fixes the test by changing the drive the missing pdb is expected to be on to C:\
instead of D:\ as that is the drive historically used to install Windows and thus
if present should be a hard drive.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D92787
2020-12-07 16:36:58 -08:00
Yaxun (Sam) Liu
59377c56bc [clang][AMDGPU] rename sram-ecc as sramecc
As backend renamed sram-ecc to sramecc, this patch makes
corresponding change in clang.

Differential Revision: https://reviews.llvm.org/D86217
2020-12-07 18:05:47 -05:00
Jessica Paquette
815bca61f5 [AArch64][GlobalISel] Narrow 128-bit regs to 64-bit regs in emitTestBit
When we have a 128-bit register, emitTestBit would incorrectly narrow to 32
bits always. If the bit number was > 32, then we would need a TB(N)ZX. This
would cause a crash, as we'd have the wrong register class. (PR48379)

This generalizes `narrowExtReg` into `moveScalarRegClass`.

This also allows us to remove `widenGPRBankRegIfNeeded` entirely, since
`selectCopy` correctly handles SUBREG_TO_REG etc.

This does create some codegen changes (since `selectCopy` uses the `all`
regclass variants). However, I think that these will likely be optimized away,
and we can always improve the `selectCopy` code. It looks like we should
revisit `selectCopy` at this point, and possibly refactor it into at least one
`emit` function.

Differential Revision: https://reviews.llvm.org/D92707
2020-12-07 15:04:33 -08:00
Philip Reames
68207a0a0f Teach isKnownNonEqual how to recurse through invertible multiplies
Build on the work started in 8f07629, and add the multiply case. In the process, more clearly describe the requirement for the operation we're looking through.

Differential Revision: https://reviews.llvm.org/D92726
2020-12-07 14:52:08 -08:00
wlei
db7fa377e4 [CSSPGO][llvm-profgen] Context-sensitive profile data generation
This stack of changes introduces `llvm-profgen` utility which generates a profile data file from given perf script data files for sample-based PGO. It’s part of(not only) the CSSPGO work. Specifically to support context-sensitive with/without pseudo probe profile, it implements a series of functionalities including perf trace parsing, instruction symbolization, LBR stack/call frame stack unwinding, pseudo probe decoding, etc. Also high throughput is achieved by multiple levels of sample aggregation and compatible format with one stop is generated at the end. Please refer to: https://groups.google.com/g/llvm-dev/c/1p1rdYbL93s for the CSSPGO RFC.

This change supports context-sensitive profile data generation into llvm-profgen. With simultaneous sampling for LBR and call stack, we can identify leaf of LBR sample with calling context from stack sample . During the process of deriving fall through path from LBR entries, we unwind LBR by replaying all the calls and returns (including implicit calls/returns due to inlining) backwards on top of the sampled call stack. Then the state of call stack as we unwind through LBR always represents the calling context of current fall through path.

we have two types of virtual unwinding 1) LBR unwinding and 2) linear range unwinding.
Specifically, for each LBR entry which can be classified into call, return, regular branch, LBR unwinding will replay the operation by pushing, popping or switching leaf frame towards the call stack and since the initial call stack is most recently sampled, the replay should be in anti-execution order, i.e. for the regular case, pop the call stack when LBR is call, push frame on call stack when LBR is return. After each LBR processed, it also needs to align with the next LBR by going through instructions from previous LBR's target to current LBR's source, which we named linear unwinding. As instruction from linear range can come from different function by inlining, linear unwinding will do the range splitting and record counters through the range with same inline context.

With each fall through path from LBR unwinding, we aggregate each sample into counters by the calling context and eventually generate full context sensitive profile (without relying on inlining) to driver compiler's PGO/FDO.

A breakdown of noteworthy changes:
- Added `HybridSample` class as the abstraction perf sample including LBR stack and call stack
* Extended `PerfReader` to implement auto-detect whether input perf script output contains CS profile, then do the parsing. Multiple `HybridSample` are extracted
* Speed up by aggregating  `HybridSample` into `AggregatedSamples`
* Added VirtualUnwinder that consumes aggregated  `HybridSample` and implements unwinding of calls, returns, and linear path that contains implicit call/return from inlining. Ranges and branches counters are aggregated by the calling context.
 Here calling context is string type, each context is a pair of function name and callsite location info, the whole context is like `main:1 @ foo:2 @ bar`.
* Added PorfileGenerater that accumulates counters by ranges unfolding or branch target mapping, then generates context-sensitive function profile including function body, inferring callee's head sample, callsite target samples, eventually records into ProfileMap.

* Leveraged LLVM build-in(`SampleProfWriter`) writer to support different serialization format with no stop
- `getCanonicalFnName` for callee name and name from ELF section
- Added regression test for both unwinding and profile generation

Test Plan:
ninja & ninja check-llvm

Reviewed By: hoy, wenlei, wmi

Differential Revision: https://reviews.llvm.org/D89723
2020-12-07 13:48:58 -08:00
Alex Zinenko
3d570da2a1 [OpenMPIRBuilder] introduce createStaticWorkshareLoop
Introduce a function that creates a statically-scheduled workshare loop
out of a canonical loop created earlier by the OpenMPIRBuilder. This
basically amounts to injecting runtime calls to the preheader and the
after block and updating the trip count. Static scheduling kind is
currently hardcoded and needs to be extracted from the runtime library
into common TableGen definitions.

Differential Revision: https://reviews.llvm.org/D92476
2020-12-07 22:30:59 +01:00
Amy Huang
1dae873326 [CodeView] Fix inline sites that are missing code offsets.
When an inline site has a starting code offset of 0, we sometimes
don't emit the starting offset.

Bug: https://bugs.llvm.org/show_bug.cgi?id=48377

Differential Revision: https://reviews.llvm.org/D92590
2020-12-07 13:01:53 -08:00
Nico Weber
2e1a73029c docs: Add pointer to cmake caches for PGO
Also add a link to end-user PGO documentation.

Differential Revision: https://reviews.llvm.org/D92768
2020-12-07 15:55:26 -05:00
Amara Emerson
f32831c4e9 [AArch64] Fix some minor coding style issues in AArch64CompressJumpTables 2020-12-07 12:48:09 -08:00
Nathan James
28b9fcb9d6 [llvm][NFC] Made RefCountBase constructors protected
Matches ThreadSafeRefCountBase and forces the class to be inherited.
2020-12-07 20:23:11 +00:00
Nathan James
d6790a9df8 [llvm] Add asserts in (ThreadSafe)?RefCountedBase destructors
Added a trivial destructor in release mode and in debug mode a destructor that asserts RefCount is indeed zero.
This ensure people aren't manually (maybe accidentally) destroying these objects like in this contrived example.
```lang=c++
{
  std::unique_ptr<SomethingRefCounted> Object;
  holdIntrusiveOwnership(Object.get());
  // Object Destructor called here will assert.
}
```

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D92480
2020-12-07 20:20:08 +00:00
Derek Schuff
24b9266a7e [WebAssembly] Add Object and ObjectWriter support for wasm COMDAT sections
Allow sections to be placed into COMDAT groups, in addtion to functions and data
segments.

Also make section symbols unnamed, which allows sections with identical names
(section names are independent of their section symbols, but previously we
gave the symbols the same name as their sections, which results in collisions
when sections are identically-named).

Differential Revision: https://reviews.llvm.org/D92691
2020-12-07 12:12:44 -08:00
Sanjay Patel
98a0dc8d53 [SLP] fix typo in debug string; NFC 2020-12-07 15:09:21 -05:00
Bardia Mahjour
2c6f4bdbb7 [LV] Epilogue Vectorization with Optimal Control Flow - Default Enablement
This patch enables epilogue vectorization by default per reviewer requests.

Differential Revision: https://reviews.llvm.org/D89566
2020-12-07 14:29:36 -05:00
Valentin Clement
c5506c705e [flang][openacc] Add clause validity tests for the kernels directive
Add some clause validity tests for the kernels directive

Reviewed By: sameeranjoshi

Differential Revision: https://reviews.llvm.org/D91873
2020-12-07 14:27:18 -05:00
Stanislav Mekhanoshin
a42643fc75 [AMDGPU] Annotate vgpr<->agpr spills in asm
Differential Revision: https://reviews.llvm.org/D92125
2020-12-07 11:25:25 -08:00
Florian Hahn
4b1d72bba8 [ConstraintElimination] Tweak placement in pipeline.
This patch adds the ConstraintElimination pass to the LTO pipeline and
also runs it after SCCP in the function simplification pipeline.

This increases the number of cases we can elimination. Pending further
tuning.
2020-12-07 19:08:40 +00:00
Stefan Pintilie
e4e35775d8 [PowerPC] Exploitation of xxeval instruction for AND and NAND
The xxeval instruction was intorduced in Power PC in Power 10.
The instruction accepts three vector registers and an immediate.
Depending on the value of the immediate the instruction can be used
to perform certain bitwise boolean operations (and, or, xor, ...) on
the given vector registers.

This patch implements the AND and NAND patterns that can be used by
the instruction.

Reviewed By: nemanjai, #powerpc, bsaleil, NeHuang, jsji

Differential Revision: https://reviews.llvm.org/D92420
2020-12-07 12:36:54 -06:00
Craig Topper
6f41d7a87b [RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X).
A rotate by half the bitwidth swaps the bottom and top half which is the same as one of the MSB GREVI stage.

We have to do this as a special combine because we prefer to keep (rotl/rotr X, BitWidth/2) as a rotate rather than a single stage GREVI.

Differential Revision: https://reviews.llvm.org/D92286
2020-12-07 10:28:04 -08:00
Simon Pilgrim
da119a17e3 [X86] Fix static analyzer warnings. NFCI.
Replace '|' with '||' in condition, and fix case of SignedMode variable.
2020-12-07 18:23:55 +00:00
Simon Pilgrim
b73408278e [DAG] Cleanup by folding some single use VT.getScalarSizeInBits() calls into its comparison. NFCI. 2020-12-07 18:23:54 +00:00
Simon Pilgrim
cf86ed0017 [IPO] Fix operator precedence warning. NFCI.
Check the entire assertion condition before && with the message.
2020-12-07 18:23:54 +00:00
Anton Afanasyev
6e271cdf29 [SLP][Test] Add test for PR46983 2020-12-07 21:07:40 +03:00
Hans Wennborg
0bc6a17a7e Test commit 2020-12-07 17:27:03 +01:00
Alexey Bataev
a5cc9d0a29 [SLP]Merge reorder and reuse shuffles.
It is possible to merge reuse and reorder shuffles and reduce the total
cost of the ivectorization tree/number of final instructions.

Differential Revision: https://reviews.llvm.org/D92668
2020-12-07 07:50:00 -08:00
David Green
89eb63dc4e [ARM] Revert low overhead loops with calls before registry allocation.
This adds code to revert low overhead loops with calls in them before
register allocation. Ideally we would not create low overhead loops with
calls in them to begin with, but that can be difficult to always get
correct. If we want to try and glue together t2LoopDec and t2LoopEnd
into a single instruction, we need to ensure that no instructions use LR
in the loop. (Technically the final code can be better too, as it
doesn't need to use the same registers but that has not been optimized
for here, as reverting loops with calls is expected to be very rare).

It also adds a MVETailPredUtils.h header to share the revert code
between different passes, and provides a place to expand upon, with
RevertLoopWithCall becoming a place to perform other low overhead loop
alterations like removing copies or combining LoopDec and End into a
single instruction.

Differential Revision: https://reviews.llvm.org/D91273
2020-12-07 15:44:40 +00:00
Andy Wingo
b570ac6d14 [WebAssembly][MC] Fix placement of table section
The table section goes after functions.

Differential Revision: https://reviews.llvm.org/D92323
2020-12-07 16:17:32 +01:00
Jinsong Ji
2f4691db5e [PowerPC][Clang] Remove QPX support
Clean up QPX code in clang missed in https://reviews.llvm.org/D83915

Reviewed By: #powerpc, steven.zhang

Differential Revision: https://reviews.llvm.org/D92329
2020-12-07 10:15:39 -05:00
Alexey Bataev
86c17d782b [SLP]Update test checks, NFC. 2020-12-07 06:12:05 -08:00
Kazushi (Jam) Marukawa
a1f04fca4d [VE] Add vcp and vex intrinsic instructions
Add vcp and vex intrinsic instructions and regression tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D92752
2020-12-07 22:56:55 +09:00