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Commit Graph

48463 Commits

Author SHA1 Message Date
Jim Grosbach
9ffa43becc ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests.

llvm-svn: 135797
2011-07-22 20:18:21 +00:00
Jim Grosbach
4f1031662f ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.

llvm-svn: 135796
2011-07-22 20:11:20 +00:00
Bruno Cardoso Lopes
5382a1e65e Add v8f32->v8i32 bitcast. Fixes PR10440
llvm-svn: 135794
2011-07-22 19:51:02 +00:00
Rafael Espindola
0c8190c4a3 Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64
too. Patch by Jeff Muizelaar.

llvm-svn: 135789
2011-07-22 18:56:05 +00:00
Dan Gohman
734f165c30 Fix x86's XALUO lowering to return its replacement values instead
of doing the RAUW calls for the overflow value itself. This makes
it more consistent with how the rest of LegalizeDAG works.

llvm-svn: 135788
2011-07-22 18:45:15 +00:00
Owen Anderson
42c1cb92e5 Fix test failures caused by my so_reg refactoring.
llvm-svn: 135785
2011-07-22 18:30:30 +00:00
Jim Grosbach
ebd66f344c ARM assembly parsing and encoding for SMC instruction.
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
Jim Grosbach
c80a7c4e75 Clean up a few more comments.
These instruction definitions are for the assembler, too, not just the
disassembler.

llvm-svn: 135781
2011-07-22 18:06:01 +00:00
Jim Grosbach
8168e689c0 Tidy up.
llvm-svn: 135779
2011-07-22 18:04:10 +00:00
Jim Grosbach
bab60c95e1 Thumb assembly support for SETEND instruction.
llvm-svn: 135778
2011-07-22 17:52:23 +00:00
Jim Grosbach
98e7733a08 Tidy up.
llvm-svn: 135777
2011-07-22 17:46:13 +00:00
Jim Grosbach
0fe45ec0ed ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.

llvm-svn: 135776
2011-07-22 17:44:50 +00:00
Jim Grosbach
97f089a499 Tidy up.
llvm-svn: 135771
2011-07-22 16:59:04 +00:00
Jay Foad
5ceaa632f9 Fix more MSVC warnings caused by a cases I missed when converting
ConstantExpr::getGetElementPtr to use ArrayRef.

llvm-svn: 135762
2011-07-22 08:52:50 +00:00
Jay Foad
42463ed852 Convert IRBuilder::CreateGEP and IRBuilder::CreateInBoundsGEP to use
ArrayRef.

llvm-svn: 135761
2011-07-22 08:16:57 +00:00
Chandler Carruth
ace8fa5233 Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs.
The header file was already properly located. The previous need for it
in Support had to do with the version string printing which was fixed in
r135757.

Also update build dependencies where libraries that needed the
functionality of the Target library (in the form of the TargetRegistry)
were picking it up via Support. This is pretty pervasive, essentially
every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it
depend on Target. All of these were previously just sneaking by.

llvm-svn: 135760
2011-07-22 08:16:53 +00:00
Jay Foad
e12d8629a8 Fix an MSVC warning, caused by a case I missed when converting
ConstantExpr::getGetElementPtr to use ArrayRef.

llvm-svn: 135758
2011-07-22 07:54:01 +00:00
Chandler Carruth
9df16051f4 Move the registered target printing in version strings completely out of
the Support library. Now its part of the TargetRegistry, and the three
commands that care about this explicitly register this extra bit of
version information.

The set of commands which care was computed by intersecting those which
use the Support library's version string printing and those that
initialize all the registered targets in a way that produces
a meaningful list. The only odd ball out is that 'clang -cc1as -version'
no longer prints the registered targets. I don't think anyone is really
interested in that (especially as the fact that llvm-mc does so is under
a FIXME), but if someone really does want this back I'll happily apply
the same patch there.

llvm-svn: 135757
2011-07-22 07:50:48 +00:00
Chandler Carruth
0ad63a1326 Move the logic for printing the registered targets into a static
function on the TargetRegistry. Also clean it up and use the modern LLVM
utility libraries available instead of rolling a few things manually.

llvm-svn: 135756
2011-07-22 07:50:44 +00:00
Chandler Carruth
6931004b83 Add an extension point to the CommandLine library where clients can
register extra version information to be printed. This is designed to
allow those tools which link in various targets to also print those
registered targets under --version.

Currently this printing logic is embedded into the Support library
directly; a huge layering violation. This is the first step to hoisting
it out into the tools without adding lots of duplicated code.

llvm-svn: 135755
2011-07-22 07:50:40 +00:00
NAKAMURA Takumi
b5d972a8c9 lib/Support/Triple.cpp: Recognize "-march=ppc32" to llc properly, as quick hack.
FIXME: There is an inconsistency. llvm::Triple does not understand "ppc32" and PowerPC/TargetInfo holds "ppc32".
llvm-svn: 135745
2011-07-22 04:02:22 +00:00
Jakub Staszak
cf5ebedf56 Allow getBlockFreq to return 0.
llvm-svn: 135742
2011-07-22 02:24:57 +00:00
Benjamin Kramer
d63be39648 GCC complains about the angle of this line.
Remove the escaped newline.

llvm-svn: 135739
2011-07-22 01:02:57 +00:00
Jakub Staszak
50b63cc04e Revert patch which broke some IfConversion tests.
llvm-svn: 135738
2011-07-22 00:55:15 +00:00
Jakub Staszak
193dd197eb Fix typo in #include which revealed in the case-sensitive filesystem.
llvm-svn: 135734
2011-07-22 00:39:00 +00:00
Bruno Cardoso Lopes
8f30ce017a Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn't
the way to go. Doing this here will prevent several node matches later,
and would have to force looking all the way through several
VINSERTF128/VEXTRACTF128 chains to optimize simple things.

llvm-svn: 135730
2011-07-22 00:15:10 +00:00
Bruno Cardoso Lopes
b7b9688aa5 -Inspected a AVX code block added by someone in early Feb. This was never used
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.

- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.

- Fix a fragile test and make it more useful.

llvm-svn: 135729
2011-07-22 00:15:07 +00:00
Bruno Cardoso Lopes
1ee6122518 Add a DAGCombine for transforming 128->256 casts into a simple
vxorps + vinsertf128 pair of instructions

llvm-svn: 135727
2011-07-22 00:15:00 +00:00
Bruno Cardoso Lopes
7e5f2950cc Introduce a new function to lower 256-bit vectors which are not
direclty supported and should be promoted and handled by smaller
shuffles

llvm-svn: 135726
2011-07-22 00:14:56 +00:00
Bruno Cardoso Lopes
71a17c4789 Rename function to be more specific and be more strict about its usage
llvm-svn: 135725
2011-07-22 00:14:53 +00:00
Jakub Staszak
bb1d5dc7e7 Use MachineBranchProbabilityInfo instead of MachineLoopInfo in IfConversion.
llvm-svn: 135724
2011-07-21 23:48:55 +00:00
Owen Anderson
e34471d064 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
llvm-svn: 135722
2011-07-21 23:38:37 +00:00
Dan Gohman
b320950f65 Fix MergeInVectorType to check for vector types with the same alloc
size but different element types, so that it filters out the cases
that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827.

llvm-svn: 135721
2011-07-21 23:30:09 +00:00
Jim Grosbach
e56f945492 ARM Asm parser range checking for [0,31] immediates.
llvm-svn: 135719
2011-07-21 23:26:25 +00:00
Jakub Staszak
e01d74a920 Add missing getAnalysisUsage in MachineBlockFrequency.
llvm-svn: 135714
2011-07-21 22:59:09 +00:00
Jim Grosbach
8d031eeb23 ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135713
2011-07-21 22:56:30 +00:00
Jim Grosbach
e96857fd4f ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135712
2011-07-21 22:37:43 +00:00
Jim Grosbach
724e527a7a Tidy up.
llvm-svn: 135706
2011-07-21 21:26:05 +00:00
Nicolas Geoffray
5cea57ec31 Update generated CPP code with the new API on CallInst::Create and ConstantExpr::getGetElementPtr.
llvm-svn: 135704
2011-07-21 20:59:21 +00:00
Jim Grosbach
a860ba338f ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.

llvm-svn: 135702
2011-07-21 19:57:11 +00:00
Oscar Fuentes
c951cb1ef4 Fix CMake build
llvm-svn: 135698
2011-07-21 19:10:57 +00:00
Owen Anderson
2e26de13d2 Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
llvm-svn: 135693
2011-07-21 18:54:16 +00:00
Andrew Trick
66db1adfe1 Cleanup: make std::pair usage slightly less indecipherable without actually naming variables!
llvm-svn: 135684
2011-07-21 17:37:39 +00:00
Jim Grosbach
5a0277bab7 ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
llvm-svn: 135682
2011-07-21 17:23:04 +00:00
Bruno Cardoso Lopes
6934331f4c Added the infrastructute necessary for MIPS JIT support. Patch by Vladimir
Stefanovic. I removed the part that actually emits the instructions cause
I want that to get in better shape first and in incremental steps. This
also makes it easier to review the upcoming parts.

llvm-svn: 135678
2011-07-21 16:28:51 +00:00
Jay Foad
42eb18b051 Make better use of ConstantExpr::getGetElementPtr's InBounds parameter.
llvm-svn: 135676
2011-07-21 15:15:37 +00:00
Jay Foad
d4458dd707 Convert ConstantExpr::getGetElementPtr and
ConstantExpr::getInBoundsGetElementPtr to use ArrayRef.

llvm-svn: 135673
2011-07-21 14:31:17 +00:00
Chris Lattner
c4ab50bd33 move tier out of an anonymous namespace, it doesn't make sense
to for it to be an an anon namespace and be in a header.

Eliminate some extraenous uses of tie.

llvm-svn: 135669
2011-07-21 06:21:31 +00:00
Bruno Cardoso Lopes
3691063149 - Register v16i16 as valid VR256 register class
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16

llvm-svn: 135663
2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes
ba1a2a9135 Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

llvm-svn: 135662
2011-07-21 01:55:47 +00:00